US4897150A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of direct write desposition of a conductor on a semiconductor
Assignee: Lasa Industries Inc
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Filing: 1988-06-29
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Granted: 1990-01-30
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Expires: 2008-06-29
Abstract
Abstract An improved method of patterning a conductive interconnect on a semiconductor element is disclosed. A catalytic layer of, for example, amorphous silicon is deposited on a semiconductor element. The areas over which a conductive pattern is to be formed is activated by directing a focused laser beam onto the amorphous silicon to form crystallized silicon. The amorphous silicon is then etched away after which a conductive material such as a metal is deposited on the activated crystallized silicon.
Inventors
- 👤 Daniel J. Dooley
- 👤 Arthur R. Elsea, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:06
CPC Classifications
H; H10; H10P; H10P95/00; H10P14/00; H10P14/40; H10P14/412; Y; Y10; Y10S; Y10S438/00; Y10S438/903; Y10S438/98
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
55 words
A method of forming a conductive pattern on a semiconductor element comprising the steps of: depositing a catalytic layer on said semiconductor element; activating selected regions of said catalytic layer to form a pattern of activated regions; etching the areas of said catalytic layer not activated; and depositing a conductive material on said activated regions.
Claim 2
Independent Claim
55 words
A method of forming a conductive pattern on a semiconductor element comprising the steps of: depositing a catalytic layer on said semiconductor element; activating selected regions of said catalytic layer to form a pattern of activated regions; etching the areas of said catalytic layer not activated; and depositing a conductive material on said activated regions.
Claim 3
Independent Claim
60 words
A method of forming a conductive pattern on a semiconductor element comprising the steps of: depositing a catalytic layer on said semiconductor element; activating selected regions of said catalytic layer to form a pattern of activated regions; and depositing a selective conductive material over said catalytic layer, a conductive pattern being formed on said semi conductor over said activated regions.
Claim 4
Independent Claim
60 words
A method of forming a conductive pattern on a semiconductor element comprising the steps of: depositing a catalytic layer on said semiconductor element; activating selected regions of said catalytic layer to form a pattern of activated regions; and depositing a selective conductive material over said catalytic layer, a conductive pattern being formed on said semi conductor over said activated regions.
Claim 5
Independent Claim
64 words
A method of forming a conductive pattern on a semiconductor element comprising the steps of: depositing an amorphous silicon layer on said semiconductor element; selectively heating regions of said amorphous silicon layer to form a pattern of crystallized silicon; and depositing a selective conductive material over said amorphous silicon layer including said selected regions to thereby form a conductive pattern on said crystallized silicon.
Claim 6
Independent Claim
64 words
A method of forming a conductive pattern on a semiconductor element comprising the steps of: depositing an amorphous silicon layer on said semiconductor element; selectively heating regions of said amorphous silicon layer to form a pattern of crystallized silicon; and depositing a selective conductive material over said amorphous silicon layer including said selected regions to thereby form a conductive pattern on said crystallized silicon.
Claim 7
Dependent Claim
32 words
The method of claim 3 wherein said heating step comprises the step of traversing a focused laser beam over the surface of said amorphous silicon to form a pattern of crystallized silicon.
Claim 8
Dependent Claim
16 words
The method of claim 4 wherein said amorphous silicon layer is less than about 2000 Å.
Claim 9
Dependent Claim
17 words
The method of claim 4 wherein said focused laser beam has a wavelength of about 5,145 Å.
Claim 10
Independent Claim
71 words
A method of forming a conductive pattern on a semiconductor element comprising the steps of: depositing a layer of amorphous silicon on said semiconductor element; heating selected regions of said amorphous silicon layer to form a pattern of crystallized silicon in said amorphous silicon layer; etching the non-crystallized amorphous silicon layer away; heating said substrate in the presence of WF 6 gas; and selectively depositing tungsten on said crystallized silicon regions.
Claim 11
Independent Claim
71 words
A method of forming a conductive pattern on a semiconductor element comprising the steps of: depositing a layer of amorphous silicon on said semiconductor element; heating selected regions of said amorphous silicon layer to form a pattern of crystallized silicon in said amorphous silicon layer; etching the non-crystallized amorphous silicon layer away; heating said substrate in the presence of WF 6 gas; and selectively depositing tungsten on said crystallized silicon regions.
Claim 12
Dependent Claim
30 words
The method of claim 7 wherein said heating step comprises the step of traversing a focused laser beam over the surface of said amorphous silicon to form a pattern therein.
Claim 13
Dependent Claim
35 words
The method of claim 8 wherein said amorphous silicon layer is less than about 2000 Å, and wherein said substrate is heated to a temperature of between 400° and 500° C. during said heating step.
Claim 14
Independent Claim
58 words
A method of forming a conductive pattern on an integrated circuit element comprising the steps of: depositing a thin catalytic layer on said integrated circuit; activating selected regions of said catalytic layer to form a pattern of activated regions; etching away the areas of said catalytic layer not activated; and depositing a conductive material on said activated regions.
Claim 15
Independent Claim
58 words
A method of forming a conductive pattern on an integrated circuit element comprising the steps of: depositing a thin catalytic layer on said integrated circuit; activating selected regions of said catalytic layer to form a pattern of activated regions; etching away the areas of said catalytic layer not activated; and depositing a conductive material on said activated regions.
Claim 16
Independent Claim
52 words
A method of forming a conductive pattern on an integrated circuit element comprising the steps of: depositing selected regions of a catalytic layer to form a pattern of activated regions; and depositing a conductive material over said catalytic layer, a conductive pattern being formed on said integrated circuit over said activated regions.
Claim 17
Independent Claim
52 words
A method of forming a conductive pattern on an integrated circuit element comprising the steps of: depositing selected regions of a catalytic layer to form a pattern of activated regions; and depositing a conductive material over said catalytic layer, a conductive pattern being formed on said integrated circuit over said activated regions.
Claim 18
Dependent Claim
25 words
The method of claim 11 further comprising the steps of etching away the non-activated catalytic layer, and depositing an insulator layer over said conductive pattern.
Claim 19
Independent Claim
63 words
A method of forming a conductive pattern on an integrated circuit element comprising the steps of: depositing a thin amorphous silicon a layer on said semiconductor element; selectively heating regions of said amorphous silicon to form a pattern of crystallized silicon; and depositing a conductive material over said silicon layer including said selected regions to form a conductive pattern on said crystallized silicon.
Claim 20
Independent Claim
63 words
A method of forming a conductive pattern on an integrated circuit element comprising the steps of: depositing a thin amorphous silicon a layer on said semiconductor element; selectively heating regions of said amorphous silicon to form a pattern of crystallized silicon; and depositing a conductive material over said silicon layer including said selected regions to form a conductive pattern on said crystallized silicon.
Claim 21
Dependent Claim
27 words
The method of claim 13 further comprising the step of etching away the non-crystallized silicon layer, said etching step being before or after said conductive deposition step.
Claim 22
Dependent Claim
32 words
The method of claim 13 wherein said heating step comprises the step of traversing a focused laser beam over the surface of said amorphous silicon to form a pattern of crystallized silicon.
Claim 23
Dependent Claim
16 words
The method of claim 15 wherein said amorphous silicon layer is less than about 2000 Å.
Claim 24
Dependent Claim
17 words
The method of claim 15 wherein said focused laser beam has a wavelength of about 5,145 Å.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-29 | 1993-07-31 | 1994-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-29 | 1997-07-31 | 1998-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-29 | 2001-07-31 | 2002-01-30 | $7700.00 | Window Closed / Lapsed |