US4906871A
Expired / Lapsed
US
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Level shift circuit for converting a signal in an ecl level into a signal in a cmos logic level
Assignee: Toshiba Corp
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Filing: 1988-11-25
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Granted: 1990-03-06
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Expires: 2008-11-25
Abstract
Abstract A level shift circuit is made up of a capacitor, a MOS inverter, and a bias circuit for applying a bias voltage to an input node of the MOS inverter. A first electrode of the capacitor is connected to an output stage of an ECL circuit, while a second electrode to the input node of the MOS inverter. The output node of the MOS inverter is coupled with an input stage of a CMOS circuit. An output signal of the ECL circuit is capacitively coupled with the input node of the MOS inverter so that it is superposed onto a bias voltage being supplied from the bias circuit. A level of this signal is shifted to a CMOS logic level by the MOS inverter, and then applied to the input stage of the CMOS circuit.
Inventors
- 👤 Tetsuya Iida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/02; H03K19/08; H03K19/082; H03K19/09
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
81 words
A level shift circuit for converting a signal in an ECL level into a signal in a CMOS logic level, comprising: capacitor means coupled at a first electrode with an output stage of an ECL circuit; a MOS inverter connected at an input node to a second electrode of said capacitor means and at an output node to an input stage of a CMOS circuit; and bias means for applying a bias voltage to the input node of said MOS inverter.
Claim 2
Dependent Claim
81 words
A level shift circuit for converting a signal in an ECL level into a signal in a CMOS logic level, comprising: capacitor means coupled at a first electrode with an output stage of an ECL circuit; a MOS inverter connected at an input node to a second electrode of said capacitor means and at an output node to an input stage of a CMOS circuit; and bias means for applying a bias voltage to the input node of said MOS inverter.
Claim 3
Dependent Claim
16 words
A level shift circuit according to claim 1, wherein said capacitor means includes a MOS capacitor.
Claim 4
Dependent Claim
27 words
A level shift circuit according to claim 1, wherein the bias voltage generated by said bias means is near a circuit threshold voltage of said MOS inverter.
Claim 5
Dependent Claim
29 words
A level shift circuit according to claim 1, wherein said bias means includes a resistive load connected between the input node and the output node of said MOS inverter.
Claim 6
Dependent Claim
15 words
A level shift circuit according to claim 4, wherein said resistive load includes a resistor.
Claim 7
Dependent Claim
32 words
A level shift circuit according to claim 4, wherein said resistive load includes a MOS transistor being placed in a conductive state with a gate being connected to one of power sources.
Claim 8
Dependent Claim
80 words
A level shift circuit according to claim 4, wherein said resistive load includes a first MOS transistor of a first conductivity type being in a conductive state with a gate coupled with one of power sources, and a second MOS transistor of a second conductivity type whose current path is connected in parallel with said first MOS transistor, said second MOS transistor being placed in a conductive state with connection of its gate to the other of the power sources.
Claim 9
Dependent Claim
46 words
A level shift circuit according to claim 1, wherein said bias means includes a resistor connected at a first end to the input node of said MOS inverter, and a MOS inverter whose input and output nodes are connected to a second end of said resistor.
Claim 10
Dependent Claim
16 words
A level shift circuit according to claim 1, wherein said MOS inverter includes a CMOS inverter.
Claim 11
Dependent Claim
67 words
A level shift circuit according to claim 1, wherein said MOS inverter includes a drive MOS transistor of the first conductivity whose gate is connected to the second electrode of said capacitor means and whose current path is connected at one end to one of power sources, and current supply means for supplying current to the other end of the current path of said drive MOS transistor.
Claim 12
Dependent Claim
18 words
A level shift circuit according to claim 10, wherein said current supply means includes a constant current source.
Claim 13
Dependent Claim
64 words
A level shift circuit according to claim 10, wherein said current supply means includes a load MOS transistor whose current path is connected between the other end of the current path of said drive MOS transistor and the other of the power sources, said load MOS transistor being placed in a conductive state with connection of its gate for reception with a bias voltage.
Claim 14
Dependent Claim
67 words
A level shift circuit according to claim 10, wherein said current supply means includes a load MOS transistor of the first conductivity whose current path is connected between the other end of the current path of said drive MOS transistor and the other of the power sources, said load MOS transistor being placed in a conductive state with connection of its gate with said other power source.
Claim 15
Dependent Claim
72 words
A level shift circuit according to claim 10, wherein said current supply means includes a load MOS transistor of the second conductivity whose current path is connected between the other end of the current path of said a drive MOS transistor and the other of the power sources, said load MOS transistor being placed in a conductive state with connection of its gate with the other end of said drive MOS transistor.
Claim 16
Dependent Claim
37 words
A level shift circuit according to claim 10, wherein said current supply means includes a resistor connected between the other end of the current path of said drive MOS transistor and the other of the power sources.
Claim 17
Dependent Claim
135 words
A level shift circuit according to claim 1, wherein said ECL circuit includes an output stage made up of a first resistor connected at a first end to one of the power sources, a first bipolar transistor connected at a collector to a second end of said first resistor, a second resistor connected at a first end to one of the power sources, a second bipolar transistor having a collector connected to a second end of said second resistor and an emitter connected to an emitter of said first bipolar transistor, a constant current source connected between the other of the power sources and the interconnection point of the emitters of said first and second bipolar transistors, and the first electrode of said capacitor means is connected to the collector of said first bipolar transistor.
Claim 18
Dependent Claim
34 words
A level shift circuit according to claim 1, wherein said CMOS circuit includes a CMOS inverter, and the input node of said CMOS inverter is connected to the output node of said MOS inverter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-05 | 1993-09-04 | 1994-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-05 | 1997-09-04 | 1998-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-05 | 2001-09-04 | 2002-03-06 | $7700.00 | Window Closed / Lapsed |