US4907066A
Expired / Lapsed
US
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Planar tungsten interconnect with implanted silicon
Assignee: Cornell Research Foundation Inc
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Filing: 1988-02-22
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Granted: 1990-03-06
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Expires: 2008-02-22
Abstract
Abstract A planar interconnect using selective deposition of a refractory metal such as tungsten into oxide channels is disclosed. A layer of silicon dioxide as thick as the desired tungsten interconnect is placed on the surface of a substrate such as an integrated circuit wafer. Thereafter, a layer of silicon nitride about 100 nm thick is formed on the silicon dioxide. Channels are formed in the silicon dioxide by patterning and etching the composite dielectric layers. After the photoresist is removed, silicon or tungsten atoms at 40 KeV are implanted in the silicon dioxide channels, the silicon nitride acting as a mask. Typically, a dosage as high as 1×10 17 cm -2 is used. The silicon or tungsten implant allows seeding of the tungsten or other retractory metal. The silicon nitride mask is selectively removed by a hot phosphoric acid solution, and a metal film is then selectively deposited to fill the channels in the silicon dioxide layer, which then forms a level of interconnects. The process is repeated to form vias and subsequent levels of interconnects.
Inventors
- 👤 David C. Thomas
- 👤 S. Simon Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:08
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/057; H10P; H10P14/00; H10P14/40; H10P14/412
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
128 words
A planar interconnect level for VLSI devices, comprising: a layer of silicon dioxide formed on a top planar surface of an integrated circuit wafer, said layer having a predetermined thickness and having a planar top surface; at least one interconnect channel formed in said silicon dioxide layer, said channel having side walls extending down from the top surface of said layer and having a bottom wall at a depth less than the thickness of said layers; a silicon implant layer in the bottom wall of said channel; a tungsten film in said channel in intimate bonding contact with said implant layer to form a tungsten interconnect line, said tungsten film completely filling said channel between said side walls to produce a planar top surface for said interconnect level.
Claim 2
Dependent Claim
128 words
A planar interconnect level for VLSI devices, comprising: a layer of silicon dioxide formed on a top planar surface of an integrated circuit wafer, said layer having a predetermined thickness and having a planar top surface; at least one interconnect channel formed in said silicon dioxide layer, said channel having side walls extending down from the top surface of said layer and having a bottom wall at a depth less than the thickness of said layers; a silicon implant layer in the bottom wall of said channel; a tungsten film in said channel in intimate bonding contact with said implant layer to form a tungsten interconnect line, said tungsten film completely filling said channel between said side walls to produce a planar top surface for said interconnect level.
Claim 3
Dependent Claim
67 words
The planar interconnect level of claim 1, further including a plurality of interconnect channels formed in said layer, each said interconnect channel having a silicon implant at the bottom thereof and being filled with tungsten to form adjacent tungsten interconnect lines, said channels being closely spaced and having a width and spacing dimensioned to produce a metal pitch between adjacent lines of less than about two microns.
Claim 4
Dependent Claim
24 words
The planar interconnect level of claim 2, wherein each of the plurality of tungsten interconnect lines is less than about one micron in width.
Claim 5
Dependent Claim
159 words
A planar interconnect level for VLSI devices, comprising: a layer of silicon dioxide formed on a top planar surface of an integrated circuit wafer, said layer having a predetermined thickness and a planar top surface; at least one interconnect channel formed in said silicon dioxide layer, said channel having vertical side walls extending down from the top surface of said layer and having a bottom wall at a depth less than the thickness of said layers; a silicon implant seed-enhancing layer at only the bottom wall of said channel; a metallization layer in said channel, said metallization layer being of a material which seeds on said silicon implant layer but not on said silicon dioxide, said metallization layer being bonded to said implant layer and completely filling said channel between said side walls and to a level flush with said planar top surface of said silicon dioxide layer to thereby produce a planar top surface for said interconnect level.
Claim 6
Dependent Claim
159 words
A planar interconnect level for VLSI devices, comprising: a layer of silicon dioxide formed on a top planar surface of an integrated circuit wafer, said layer having a predetermined thickness and a planar top surface; at least one interconnect channel formed in said silicon dioxide layer, said channel having vertical side walls extending down from the top surface of said layer and having a bottom wall at a depth less than the thickness of said layers; a silicon implant seed-enhancing layer at only the bottom wall of said channel; a metallization layer in said channel, said metallization layer being of a material which seeds on said silicon implant layer but not on said silicon dioxide, said metallization layer being bonded to said implant layer and completely filling said channel between said side walls and to a level flush with said planar top surface of said silicon dioxide layer to thereby produce a planar top surface for said interconnect level.
Claim 7
Dependent Claim
15 words
The planar interconnect level of claim 4, wherein said metallization layer is a refractory metal.
Claim 8
Dependent Claim
13 words
The planar interconnect level of claim 4, wherein said metallization layer is tungsten.
Claim 9
Dependent Claim
49 words
The planar interconnect level of claim 6, further including at least two interconnect channels filled with tungsten in said silicon dioxide layer, said channels being closely spaced in side-by-side relationship and having a width and spacing dimensioned to produce a metal pitch therebetween of less than about two microns.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-05 | 1993-09-04 | 1994-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-05 | 1997-09-04 | 1998-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-05 | 2001-09-04 | 2002-03-06 | $7700.00 | Window Closed / Lapsed |