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US4908327A Expired / Lapsed US ⏱️ 0.0 years remaining

Counter-doped transistor

Assignee: Texas Instruments Inc
•
Filing: 1988-05-02
•
Granted: 1990-03-13
•
Expires: 2008-05-02
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Abstract

Abstract P channel and N channel CMOS FETs (22, 24) and a process for their simultaneous fabrication with a minimal number of masking steps are disclosed. After formation of gates (30, 32) for both P channel FETs (24) and N channel FETs (22), a first N type dopant implanting step forms lightly doped drain extensions in both the P channel FETs (24) and the N channel FETs (22). A mask then protects the N channel FET area (22) while a P type dopant is implanted in source and drain regions (36) of the P channel FET (24) at a greater concentration than the prior implanted N type dopant. Another N type dopant implant occurs to both the P channel FET (24) and N channel FET (22). The N type dopant dosage used in this second N type dopant implantation step is greater than the dosage used in the first N type dopant implantation step. Another mask is used to protect the N channel FET (22) while a second P type dopant is implanted into source and drain regions of the P channel FET (24) at a greater concentration than is used in any of the previous implantation steps. Due to the high diffusion rate of the P type dopant, an annealing step drives the P type dopant so that the P channel FET (24) source and drain regions (36) reach the active transistor region underneath the gate.

Inventors

  • 👤 Richard A. Chapman

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 21:05
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S257/00; Y10S257/90

Claims Analysis

Total Claims: 21
Claim 1
Independent Claim 321 words
A method for forming a field effect transistor having lightly doped regions, comprising the steps of: providing a substrate; forming a patterned layer on said substrate; performing a first implantation of first dopant atoms into said substrate, said first dopant atoms having a characteristic of forming regions of a first conductivity type when implanted into said substrate, said patterned layer serving as a mask to prevent implantation of said first dopant atoms in said substrate; forming first spacer layers on at least one sidewall of said patterned layer; performing a second implantation of second dopant atoms into said substrate, said second dopant atoms having a characteristic of forming regions of a second conductivity type when implanted into said substrate, said patterned layer and said spacer layers serving as a mask to prevent implantation of said second dopant atoms, said second dopant atoms having a higher rate of diffusion in said substrate than said first dopant atoms; forming a second spacer layers on said first spacer layers; performing a third implantation of third dopant atoms into said substrate, said third dopant atoms having a characteristic of forming regions of a first conductivity type when implanted into said substrate, said patterned layer, said first spacer layers and said second spacer layers serving as a mask to prevent implantation of said third dopant atoms in said substrate; forming third spacer layers on said second spacer layers; performing a fourth implantation of fourth dopant atoms into said substrate, said fourth dopant atoms having a characteristic of forming regions of a second conductivity type when implanted into said substrate, said patterned layer and said first second and third spacer layers serving as a mask to prevent implantation of said fourth dopant atoms, said fourth dopant atoms having a higher rate of diffusion in said substrate than said third dopant atoms; heating said substrate to diffuse said first, second, third and fourth dopant atoms into said substrate.
Claim 2
Independent Claim 321 words
A method for forming a field effect transistor having lightly doped regions, comprising the steps of: providing a substrate; forming a patterned layer on said substrate; performing a first implantation of first dopant atoms into said substrate, said first dopant atoms having a characteristic of forming regions of a first conductivity type when implanted into said substrate, said patterned layer serving as a mask to prevent implantation of said first dopant atoms in said substrate; forming first spacer layers on at least one sidewall of said patterned layer; performing a second implantation of second dopant atoms into said substrate, said second dopant atoms having a characteristic of forming regions of a second conductivity type when implanted into said substrate, said patterned layer and said spacer layers serving as a mask to prevent implantation of said second dopant atoms, said second dopant atoms having a higher rate of diffusion in said substrate than said first dopant atoms; forming a second spacer layers on said first spacer layers; performing a third implantation of third dopant atoms into said substrate, said third dopant atoms having a characteristic of forming regions of a first conductivity type when implanted into said substrate, said patterned layer, said first spacer layers and said second spacer layers serving as a mask to prevent implantation of said third dopant atoms in said substrate; forming third spacer layers on said second spacer layers; performing a fourth implantation of fourth dopant atoms into said substrate, said fourth dopant atoms having a characteristic of forming regions of a second conductivity type when implanted into said substrate, said patterned layer and said first second and third spacer layers serving as a mask to prevent implantation of said fourth dopant atoms, said fourth dopant atoms having a higher rate of diffusion in said substrate than said third dopant atoms; heating said substrate to diffuse said first, second, third and fourth dopant atoms into said substrate.
Claim 3
Dependent Claim 12 words
A method as in claim 1 wherein said substrate comprises crystalline silicon.
Claim 4
Dependent Claim 22 words
A method as in claim 1 wherein said patterned layer comprises a conductive layer separate from said substrate by an insulating layer.
Claim 5
Dependent Claim 24 words
A method as in claim 3 wherein said conductive layer serves as a gate to control the conductivity of said substrate beneath said gate.
Claim 6
Dependent Claim 26 words
A method as in claim 1 wherein said first and third dopant atoms are the same and said second and fourth dopant atoms are the same.
Claim 7
Dependent Claim 26 words
A method as in claim 5 wherein said first dopant atoms are N type dopant atoms and said second dopant atoms are P type dopant atoms.
Claim 8
Dependent Claim 23 words
A method as in claim 6 wherein said first dopant atoms are Arsenic atoms and said second dopant atoms are Boron dopant atoms.
Claim 9
Dependent Claim 26 words
A method as in claim 1 wherein said first dopant atoms are N type dopant atoms and said second dopant atoms are P type dopant atoms.
Claim 10
Dependent Claim 23 words
A method as in claim 8 wherein said first dopant atoms are Arsenic atoms and said second dopant atoms are Boron dopant atoms.
Claim 11
Independent Claim 376 words
A method for forming a field effect transistor having lightly doped regions, comprising the steps of: providing a substrate having a first device area and a second device area; forming a patterned layer on said substrate; performing a first implantation of first dopant atoms into said substrate, said first dopant atoms having a characteristic of forming regions of a first conductivity type when implanted into said substrate, said patterned layer serving as a mask to prevent implantation of said first dopant atoms in said substrate; forming first spacer layers on at least one sidewall of said patterned layer; forming and patterning a first masking layer on said substrate, said first masking layer protecting said second device area; performing a second implantation of second dopant atoms into said substrate, said second dopant atoms having a characteristic of forming regions of a second conductivity type when implanted into said substrate, said patterned layer, said first masking layer and said spacer layers serving as a mask to prevent implantation of said second dopant atoms, said second dopant atoms having a higher rate of diffusion in said substrate than said first dopant atoms; forming second spacer layers on said first spacer layers; performing a third implantation of third dopant atoms into said substrate, said third dopant atoms having a characteristic of forming regions of said first conductivity type when implanted into said substrate, said patterned layer, said first spacer layers and said second spacer layers serving as a mask to prevent implantation of said third dopant atoms in said substrate; forming third spacer layers on said second spacer layers; forming and patterning a second masking layer on said substrate, said second masking layer protecting said second device area; performing a fourth implantation of fourth dopant atoms into said substrate, said fourth dopant atoms having a characteristic of forming regions of said second conductivity type when implanted into said substrate, said patterned layer, said second masking layer and said first, second and third spacer layers serving as a mask to prevent implantation of said fourth dopant atoms, said fourth dopant atoms having a higher rate of diffusion in said substrate than said third dopant atoms; heating said substrate to diffusion said first, second, third and fourth dopant atoms into said substrate.
Claim 12
Independent Claim 376 words
A method for forming a field effect transistor having lightly doped regions, comprising the steps of: providing a substrate having a first device area and a second device area; forming a patterned layer on said substrate; performing a first implantation of first dopant atoms into said substrate, said first dopant atoms having a characteristic of forming regions of a first conductivity type when implanted into said substrate, said patterned layer serving as a mask to prevent implantation of said first dopant atoms in said substrate; forming first spacer layers on at least one sidewall of said patterned layer; forming and patterning a first masking layer on said substrate, said first masking layer protecting said second device area; performing a second implantation of second dopant atoms into said substrate, said second dopant atoms having a characteristic of forming regions of a second conductivity type when implanted into said substrate, said patterned layer, said first masking layer and said spacer layers serving as a mask to prevent implantation of said second dopant atoms, said second dopant atoms having a higher rate of diffusion in said substrate than said first dopant atoms; forming second spacer layers on said first spacer layers; performing a third implantation of third dopant atoms into said substrate, said third dopant atoms having a characteristic of forming regions of said first conductivity type when implanted into said substrate, said patterned layer, said first spacer layers and said second spacer layers serving as a mask to prevent implantation of said third dopant atoms in said substrate; forming third spacer layers on said second spacer layers; forming and patterning a second masking layer on said substrate, said second masking layer protecting said second device area; performing a fourth implantation of fourth dopant atoms into said substrate, said fourth dopant atoms having a characteristic of forming regions of said second conductivity type when implanted into said substrate, said patterned layer, said second masking layer and said first, second and third spacer layers serving as a mask to prevent implantation of said fourth dopant atoms, said fourth dopant atoms having a higher rate of diffusion in said substrate than said third dopant atoms; heating said substrate to diffusion said first, second, third and fourth dopant atoms into said substrate.
Claim 13
Dependent Claim 66 words
A method as in claim 10 wherein said substrate includes a first well formed in said first device area having a conductivity type opposite that formed by said second dopant atoms when introduced into said substrate and a second well formed in said substrate at said second device area having a conductivity type opposite that formed by said first dopant atoms when introduced into said substrate.
Claim 14
Dependent Claim 12 words
A method as in claim 10 wherein said substrate comprises crystalline silicon.
Claim 15
Dependent Claim 22 words
A method as in claim 10 wherein said patterned layer comprises a conductive layer separated from said substrate by an insulating layer.
Claim 16
Dependent Claim 24 words
A method as in claim 13 wherein said conductive layer serves as a gate to control the conductivity of said substrate beneath said gate.
Claim 17
Dependent Claim 26 words
A method as in claim 10 wherein said first and third dopant atoms are the same and said second and fourth dopant atoms are the same.
Claim 18
Dependent Claim 26 words
A method as in claim 15 wherein said first dopant atoms are N type dopant atoms and said second dopant atoms are P type dopant atoms.
Claim 19
Dependent Claim 23 words
A method as in claim 16 wherein said first dopant atoms are Arsenic atoms and said second dopant atoms are Boron dopant atoms.
Claim 20
Dependent Claim 26 words
A method as in claim 10 wherein said first dopant atoms are N type dopant atoms and said second dopant atoms are P type dopant atoms.
Claim 21
Dependent Claim 23 words
A method as in claim 18 wherein said first dopant atoms are Arsenic atoms and said second dopant atoms are Boron dopant atoms.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-03-12 1993-09-11 1994-03-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-03-12 1997-09-11 1998-03-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-03-12 2001-09-11 2002-03-13 $7700.00 Window Closed / Lapsed

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