US4908528A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input circuit having improved noise immunity
Assignee: Philips Semiconductors Inc
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Filing: 1988-07-21
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Granted: 1990-03-13
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Expires: 2008-07-21
Abstract
Abstract An improved CMOS input circuit is disclosed. A conventional CMOS input circuit having a plurality of inverter stages is used. The improvement comprises a N-type MOS transistor with the source connected to ground potential and the drain connected to the output node of one of the inverters. A capacitor couples a ground transient to the gate of the first N-type MOS transistor. An N-type MOS transistor provides AC isolation between the input node and the gate of the first N-type MOS transistor. A similar structure is shown for a P-type transistor connected to the power source.
Inventors
- 👤 Eddy Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:48
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/165; H03K17/162; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
199 words
In an improved electronic integrated input circuit of the type having Complementary Metal Oxide Silicon (CMOS) transistors forming an input circuit, said input circuit having a plurality of inverters with each inverter having an MOS transistor of the P type and an MOS transistor of the N type, with the gate of the P-type transistor connected to an input node, its drain connected to a positive voltage source, its source connected to the drain of the N-type MOS transistor and to an output node, with the output node being the output of said inverter, the gate of the N-type MOS transistor being connected to the input node and the source of said N-type MOS transistor being connected to a ground potential; wherein said improvement comprising: a first MOS transistor means of the N type having a source, a drain, and a gate with the source connected to said ground potential, and the drain connected to the output node of said inverter; first means for capacitively coupling a ground transient to the gate of said first MOS transistor; and first pass transistor means for providing AC isolation between said input node and the gate of said first MOS transistor means.
Claim 2
Dependent Claim
199 words
In an improved electronic integrated input circuit of the type having Complementary Metal Oxide Silicon (CMOS) transistors forming an input circuit, said input circuit having a plurality of inverters with each inverter having an MOS transistor of the P type and an MOS transistor of the N type, with the gate of the P-type transistor connected to an input node, its drain connected to a positive voltage source, its source connected to the drain of the N-type MOS transistor and to an output node, with the output node being the output of said inverter, the gate of the N-type MOS transistor being connected to the input node and the source of said N-type MOS transistor being connected to a ground potential; wherein said improvement comprising: a first MOS transistor means of the N type having a source, a drain, and a gate with the source connected to said ground potential, and the drain connected to the output node of said inverter; first means for capacitively coupling a ground transient to the gate of said first MOS transistor; and first pass transistor means for providing AC isolation between said input node and the gate of said first MOS transistor means.
Claim 3
Dependent Claim
80 words
The circuit of claim 1 further comprising: a second MOS transistor means of the P type having a source, a drain, and a gate with the drain connected to said voltage source, and the source connected to the output node of said inverter; second means for coupling a voltage transient to the gate of said second MOS transistor; and second pass transistor for providing AC isolation between said input node and the gate of the said second MOS transistor means.
Claim 4
Dependent Claim
27 words
The circuit of claim 1 wherein said first coupling means comprises a capacitor connected between the gate of said first MOS transistor means and said ground potential.
Claim 5
Dependent Claim
42 words
The circuit of claim 1 wherein said first coupling means comprises a third MOS transistor of the N type having a gate connected to the gate of said first MOS transistor, a drain and a source, both connected to said ground potential.
Claim 6
Dependent Claim
27 words
The circuit of claim 2 wherein said second coupling means comprises a capacitor connected between the gate of said second MOS transistor means and said voltage source.
Claim 7
Dependent Claim
42 words
The circuit of claim 2 wherein said second coupling means comprises a fourth MOS transistor of the P type having a gate connected to the gate of said second MOS transistor, a drain and a source, both connected to said voltage source.
Claim 8
Dependent Claim
48 words
The circuit of claim 1 wherein said first pass transistor means is a first pass transistor of the N type having a gate connected to said positive voltage source, a source connected to said input node, a drain connected to the gate of said first MOS transistor means.
Claim 9
Dependent Claim
48 words
The circuit of claim 2 wherein said second pass transistor means is a second pass transistor of the N type having a gate connected to said positive voltage source, a source connected to said input node, a drain connected to the gate of said second MOS transistor means.
Claim 10
Dependent Claim
46 words
The circuit of claim 4 further comprising: a fifth MOS transistor of the N type having a gate connected to the output node of said inverter, a source connected to said ground potential and a drain connected to the gate of said first MOS transistor means.
Claim 11
Dependent Claim
46 words
The circuit of claim 5 further comprising: a sixth MOS transistor of the P type having a gate connected to the output node of said inverter, a drain connected to said voltage source and a source connected to the gate of said second MOS transistor means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-12 | 1993-09-11 | 1994-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-12 | 1997-09-11 | 1998-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-12 | 2001-09-11 | 2002-03-13 | $7700.00 | Window Closed / Lapsed |