US4912636A
Expired / Lapsed
US
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Data processing device with multiple on chip memory buses
Assignee: Texas Instruments Inc
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Filing: 1987-03-13
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Granted: 1990-03-27
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Expires: 2007-03-13
Abstract
Abstract A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microprocessor has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxillary arithmetic logic units, in parallel with one another, and which are each connected to a set of address lines in a memory bus; the two auxillary arithmetic logic unit thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus. Memory-mapped input and output functions are performed by on-chip peripherals, which are connected to a peripheral bus connected to one of the peripheral ports of the microcomputer. The peripheral bus allows for substantial flexibility relative to the configuration of the microcomputer.
Inventors
- 👤 Surendar S. Magar
- 👤 James F. Potts
- 👤 Jerald G. Leach
- 👤 L. Ray Simar Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:41
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1684
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
200 words
A data processing device, comprising: a first memory bus for communicating address and data signals; a second memory bus for communicating address and data signals; a first memory, connected to said first memory bus and to said second memory bus, and comprising a plurality of memory locations addressable by address signals having a value within a first set of addresses; a second memory, connected to said first memory bus and to said second memory bus, and comprising a plurality of memory locations addressable by address signals having a value within a second set of addresses, said second set of addresses not overlapping any of the addresses in said first set of addresses; an arithmetic logic unit, connected to said first memory bus, for executing arithmetic and logical operations on data, said data received on said first memory bus responsive to address signals presented by said arithmetic logic unit on said first memory bus; and a controller, connected to said second memory bus and to said arithmetic logic unit, for controlling said arithmetic logic unit according to instruction codes, said instruction codes received on said second memory bus responsive to address signals presented by said controller on said second memory bus.
Claim 2
Dependent Claim
200 words
A data processing device, comprising: a first memory bus for communicating address and data signals; a second memory bus for communicating address and data signals; a first memory, connected to said first memory bus and to said second memory bus, and comprising a plurality of memory locations addressable by address signals having a value within a first set of addresses; a second memory, connected to said first memory bus and to said second memory bus, and comprising a plurality of memory locations addressable by address signals having a value within a second set of addresses, said second set of addresses not overlapping any of the addresses in said first set of addresses; an arithmetic logic unit, connected to said first memory bus, for executing arithmetic and logical operations on data, said data received on said first memory bus responsive to address signals presented by said arithmetic logic unit on said first memory bus; and a controller, connected to said second memory bus and to said arithmetic logic unit, for controlling said arithmetic logic unit according to instruction codes, said instruction codes received on said second memory bus responsive to address signals presented by said controller on said second memory bus.
Claim 3
Dependent Claim
45 words
The data processing device of claim 1, further comprising: a peripheral port, connected to said first memory bus and to said second memory bus, for presenting address signals and for presenting and receiving data signals to and from external terminals of said data processing device.
Claim 4
Dependent Claim
47 words
The data processing device of claim 2, wherein said peripheral port presents on said external terminals only address signals having a value within a third set of addresses, said third set of addresses not overlapping either said first set of addresses or said second set of addresses.
Claim 5
Dependent Claim
78 words
The data processing device of claim 1, further comprising: memory control logic, connected to said first memory, and to said first and second memory buses, for disconnecting said first memory from said one of said memory buses if the address signal presented by said first memory bus and the address signal presented by said second memory bus are both within said first set of values, said disconnected one of said memory buses determined according to a predetermined priority.
Claim 6
Dependent Claim
79 words
The data processing device of claim 4, wherein said memory control logic is also connected to said second memory; and wherein said memory control logic is also for disconnecting said second memory from one of said memory buses if the address signal presented by said first memory bus and the address signal presented by said second memory bus are both within said second set of values, said disconnected one of said memory buses determined according to a predetermined priority.
Claim 7
Dependent Claim
85 words
The data processing device of claim 5, further comprising: a peripheral port, connected to said first memory bus and to said second memory bus, for presenting address signals and for presenting and receiving data signals to and from external terminals of said data processing device; wherein said peripheral port presents on said external terminals only address signals having a value within a third set of addresses, said third set of addresses not overlapping either said first set of addresses or said second set of addresses.
Claim 8
Dependent Claim
79 words
The data processing device of claim 6, wherein said memory control logic is also connected to said peripheral port; and wherein said memory control logic is also for disconnecting said peripheral port from one of said memory buses if the address signal presented by said first memory bus and the address signal presented by said second memory bus are both within said third set of values, said disconnected one of said memory buses determined according to a predetermined priority.
Claim 9
Dependent Claim
63 words
The data processing device of claim 1, further comprising: memory control logic, connected to said first memory, and to said first and second memory buses, for disconnecting said first memory from said second memory bus if the address signal presented by said first memory bus and the address signal presented by said second memory bus are both within said first set of values.
Claim 10
Dependent Claim
65 words
The data processing device of claim 8, wherein said memory control logic is also connected to said second memory; and wherein said memory control logic is also for disconnecting said second memory from said second memory bus if the address signal presented by said first memory bus and the address signal presented by said second memory bus are both within said second set of values.
Claim 11
Dependent Claim
16 words
The data processing device of claim 1, wherein said first memory is a random access memory.
Claim 12
Dependent Claim
15 words
The data processing device of claim 1, wherein said first memory is a read-only memory.
Claim 13
Dependent Claim
16 words
The data processing device of claim 11, wherein said second memory is a random access memory.
Claim 14
Dependent Claim
258 words
A data processing device, comprising: a first memory bus for communicating address and data signals; a second memory bus for communicating address and data signals; a third memory bus for communicating address and data signals; a first memory, connected to said first, second and third memory buses, and comprising a plurality of memory locations addressable by address signals having a value within a first set of addresses; a second memory, connected to said first, second and third memory buses, and comprising a plurality of memory locations addressable by address signals having a value within a second set of addresses, said second set of addresses not overlapping any of the addresses in said first set of addresses; an arithmetic logic unit, connected to said first memory bus, for executing arithmetic and logical operations on data, said data received on said first memory bus responsive to address signals presented by said arithmetic logic unit on said first memory bus; a controller, connected to said second memory bus and to said arithmetic logic unit, for controlling said arithmetic logic unit according to instruction codes, said instruction codes received on said second memory bus responsive to address signals presented by said controller on said second memory bus; and a direct memory access controller, connected to said third memory bus, for communicating data between memory locations in said first and second memories via said third memory bus, said memory locations in said first and second memories addressed according to address signals presented by said direct memory access controller on said third memory bus.
Claim 15
Dependent Claim
258 words
A data processing device, comprising: a first memory bus for communicating address and data signals; a second memory bus for communicating address and data signals; a third memory bus for communicating address and data signals; a first memory, connected to said first, second and third memory buses, and comprising a plurality of memory locations addressable by address signals having a value within a first set of addresses; a second memory, connected to said first, second and third memory buses, and comprising a plurality of memory locations addressable by address signals having a value within a second set of addresses, said second set of addresses not overlapping any of the addresses in said first set of addresses; an arithmetic logic unit, connected to said first memory bus, for executing arithmetic and logical operations on data, said data received on said first memory bus responsive to address signals presented by said arithmetic logic unit on said first memory bus; a controller, connected to said second memory bus and to said arithmetic logic unit, for controlling said arithmetic logic unit according to instruction codes, said instruction codes received on said second memory bus responsive to address signals presented by said controller on said second memory bus; and a direct memory access controller, connected to said third memory bus, for communicating data between memory locations in said first and second memories via said third memory bus, said memory locations in said first and second memories addressed according to address signals presented by said direct memory access controller on said third memory bus.
Claim 16
Dependent Claim
113 words
The data processing device of claim 13, further comprising: a peripheral port, connected to said first, second and third memory buses, for presenting address signals and for presenting and receiving data signals to and from external terminals of said data processing device; wherein said peripheral port presents on said external terminals only address signals having a value within a third set of addresses, said third set of addresses not overlapping either said first set of addresses or said second set of addresses; and wherein said direct memory access controller is also for communicating data, via said third memory bus, between said peripheral port and said memory locations in said first and second memories.
Claim 17
Dependent Claim
74 words
The data processing device of claim 14, further comprising: memory control logic, connected to said first memory, and to said first and third memory buses, for disconnecting said first memory from either said first memory bus or said third memory bus according to a predetermined priority, if the address signal presented by said first memory bus and the address signal presented by said third memory bus are both within said first set of values.
Claim 18
Dependent Claim
76 words
The data processing device of claim 15, wherein said memory control logic is also connected to said peripheral port; and wherein said memory control logic is also for disconnecting said peripheral port from either said first memory bus or said third memory bus according to a predetermined priority, if the address signal presented by said first memory bus and the address signal presented by said third memory bus are both within said third set of values.
Claim 19
Dependent Claim
76 words
The data processing device of claim 16, wherein said memory control logic is also connected to said second memory; and wherein said memory control logic is also for disconnecting said second memory from either said first memory bus or said third memory bus according to a predetermined priority, if the address signal presented by said first memory bus and the address signal presented by said third memory bus are both within said second set of values.
Claim 20
Dependent Claim
170 words
A data processing device, comprising: at least two buses each having address lines and data lines; a plurality of memories having a memory addressing port connected to the address lines of each of the buses and the memories further having memory data port means connected to the data lines of each of the buses for coupling a given memory to the data lines of a particular bus among said buses having the address lines along which the given memory is addressed at a given time; a digital logic circuit connected to said address lines and said data lines of a first one of the buses; and controller means connected to said address lines and said data lines of a second one of the buses for accessing any of said memories, said digital logic circuit including means for selectively accessing any of said memories by the first one of said buses simultaneously with said controller means independently accessing a different one of said memories by said second one of said buses.
Claim 21
Dependent Claim
170 words
A data processing device, comprising: at least two buses each having address lines and data lines; a plurality of memories having a memory addressing port connected to the address lines of each of the buses and the memories further having memory data port means connected to the data lines of each of the buses for coupling a given memory to the data lines of a particular bus among said buses having the address lines along which the given memory is addressed at a given time; a digital logic circuit connected to said address lines and said data lines of a first one of the buses; and controller means connected to said address lines and said data lines of a second one of the buses for accessing any of said memories, said digital logic circuit including means for selectively accessing any of said memories by the first one of said buses simultaneously with said controller means independently accessing a different one of said memories by said second one of said buses.
Claim 22
Independent Claim
128 words
A method of operating a data processing device having memory buses each having address lines and data lines, and memories each connected to the address lines and data lines of the memory buses, the method comprising the steps of: accessing any one of the memories at a given time as a selected memory via the address lines of a first one of the buses; presenting data to or receiving data from said selected memory via the data lines of a particular bus among the memory buses having the address lines along which the selected memory is addressed at said given time; and accessing any other of said memories via a second one of the buses simultaneously with accessing said selected memory via the first one of the buses.
Claim 23
Independent Claim
128 words
A method of operating a data processing device having memory buses each having address lines and data lines, and memories each connected to the address lines and data lines of the memory buses, the method comprising the steps of: accessing any one of the memories at a given time as a selected memory via the address lines of a first one of the buses; presenting data to or receiving data from said selected memory via the data lines of a particular bus among the memory buses having the address lines along which the selected memory is addressed at said given time; and accessing any other of said memories via a second one of the buses simultaneously with accessing said selected memory via the first one of the buses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-26 | 1993-09-25 | 1994-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-26 | 1997-09-25 | 1998-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-26 | 2001-09-25 | 2002-03-27 | $7700.00 | Window Closed / Lapsed |