US4920512A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile semiconductor memory capable of readily erasing data
Assignee: Mitsubishi Electric Corp
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Filing: 1988-06-28
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Granted: 1990-04-24
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Expires: 2008-06-28
Abstract
Abstract An EPROM in which data can be easily erased comprises a P type semiconductor substrate; source.drain regions formed on a main surface of the P type semiconductor substrate, a floating gate for storing charges representing information formed on a region sandwiched by the source.drain regions with an insulating film interposed therebetween, a superconductive material which will be the switching device formed on the floating gate, and a control gate formed on the superconductive material. In the normal operation, the superconductive material is non-conductive, so that the charges representing information are held in the floating gate. When the charges representing information in the floating gate should be erased, the whole EPROM is cooled, and the charges are discharged through the superconductive material and the control gate. By the use of a superconducting material in this fashion, other structures enabling erasure such as UV-radiation windows and tunnel oxide films may be omitted without increasing the chip area of the non-volatile memory.
Inventors
- 👤 Hiroshi Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:31
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/06; G11C16/10; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
109 words
A non-volatile semiconductor memory comprising: a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type; impurity regions of a second conductivity type formed spaced apart from each other on the main surface of said semiconductor substrate, an area between said impurity regions of the second conductivity type defining a channel region; a first conductive layer formed at least on said channel region with an insulating film interposed therebetween; a second conductive layer formed on said first conductive layer with an insulating film interposed therebetween; and switching means comprising a superconductive material for connecting said first conductive layer and said second conductive layer.
Claim 2
Dependent Claim
109 words
A non-volatile semiconductor memory comprising: a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type; impurity regions of a second conductivity type formed spaced apart from each other on the main surface of said semiconductor substrate, an area between said impurity regions of the second conductivity type defining a channel region; a first conductive layer formed at least on said channel region with an insulating film interposed therebetween; a second conductive layer formed on said first conductive layer with an insulating film interposed therebetween; and switching means comprising a superconductive material for connecting said first conductive layer and said second conductive layer.
Claim 3
Dependent Claim
38 words
A non-volatile semiconductor memory according to claim 1, wherein said superconductive material is formed on and in contact with said first conductive layer, and said third conductive layer is formed on and in contact with said superconductive material.
Claim 4
Dependent Claim
16 words
A non-volatile semiconductor memory according to claim 2, wherein said non-volatile semiconductor memory comprises an EPROM.
Claim 5
Dependent Claim
16 words
A non-volatile semiconductor memory according to claim 2, wherein said non-volatile semiconductor memory comprises an EEPROM.
Claim 6
Dependent Claim
19 words
A non-volatile semiconductor memory according to claim 1 wherein said second conductive layer is held at a prescribed potential.
Claim 7
Dependent Claim
26 words
A non-volatile semiconductor memory according to claim 1, further including a third conductive layer extending near said first conductive layer and held at a prescribed potential.
Claim 8
Dependent Claim
67 words
A floating gate memory device comprising: a floating gate of polycrystalline silicon; a switching device formed of a superconductive material formed on and in contact with said floating gate; and a control gate of polycrystalline silicon formed on and in contact with said switching device; whereby discharge of electrons from said floating gate is carried out through said control gate by the operation of said switching device.
Claim 9
Dependent Claim
67 words
A floating gate memory device comprising: a floating gate of polycrystalline silicon; a switching device formed of a superconductive material formed on and in contact with said floating gate; and a control gate of polycrystalline silicon formed on and in contact with said switching device; whereby discharge of electrons from said floating gate is carried out through said control gate by the operation of said switching device.
Claim 10
Independent Claim
86 words
A method of controlling the storage of charge in a floating gate of a memory device having a switching device formed of a superconductive material formed on and in contact with said floating gate and a control gate formed on and in contact with said switching device comprising the steps of: applying a predetermined potential to said control gate; and subjecting the entire memory device to a temperature of a value which alters the conductive property of said superconductive material to thereby actuate said switching device.
Claim 11
Independent Claim
86 words
A method of controlling the storage of charge in a floating gate of a memory device having a switching device formed of a superconductive material formed on and in contact with said floating gate and a control gate formed on and in contact with said switching device comprising the steps of: applying a predetermined potential to said control gate; and subjecting the entire memory device to a temperature of a value which alters the conductive property of said superconductive material to thereby actuate said switching device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-23 | 1993-10-23 | 1994-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-23 | 1997-10-23 | 1998-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-23 | 2001-10-23 | 2002-04-24 | $7700.00 | Window Closed / Lapsed |