US4924315A
Expired / Lapsed
US
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Video signal processing system
Assignee: Yamashita Denshi Sekkei KK
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Filing: 1989-02-28
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Granted: 1990-05-08
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Expires: 2009-02-28
Abstract
Abstract The video signals outputted from a computer in a format of sequential scanning are memorized in a frame memory after being processed so that the isolated luminance signals do not exist in each horizontal scanning line. Furthermore, the video signals are read out from the frame memory in a format of interlaced scanning.
Inventors
- 👤 Yasushi Yamashita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:46
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/01; H04N7/0117; H04N7/012
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
170 words
A video signal processing system comprising: a processing circuit for processing input video signals including isolated luminance signals, in a format of sequential scanning so that each horizontal scanning line of the video signals does not include the isolated luminance signals, a memory for storing the video signals processed by the processing circuit, and a reading means for reading out the video signals stored in the memory and generating video signals in a format of interlaced scanning, wherein the processing circuit comprises: a first delaying circuit for delaying the input video signals by one horizontal scanning period, a second delaying circuit for delaying by one horizontal scanning period the video signal delayed by the first delaying circuit, a first coefficient multiplier for multiplying the input video signals by a first coefficient, a second coefficient multiplier for multiplying the video signals delayed by the second delaying circuit by a second coefficient, and an adding circuit for adding the outputs from the first and second coefficient multipliers and the first delaying circuit.
Claim 2
Dependent Claim
170 words
A video signal processing system comprising: a processing circuit for processing input video signals including isolated luminance signals, in a format of sequential scanning so that each horizontal scanning line of the video signals does not include the isolated luminance signals, a memory for storing the video signals processed by the processing circuit, and a reading means for reading out the video signals stored in the memory and generating video signals in a format of interlaced scanning, wherein the processing circuit comprises: a first delaying circuit for delaying the input video signals by one horizontal scanning period, a second delaying circuit for delaying by one horizontal scanning period the video signal delayed by the first delaying circuit, a first coefficient multiplier for multiplying the input video signals by a first coefficient, a second coefficient multiplier for multiplying the video signals delayed by the second delaying circuit by a second coefficient, and an adding circuit for adding the outputs from the first and second coefficient multipliers and the first delaying circuit.
Claim 3
Dependent Claim
36 words
A video signal processing system according to claim 1, wherein the video signal processing system further comprises a detecting circuit for detecting the correlation between the two sequential horizontal scanning lines of the input video signals.
Claim 4
Dependent Claim
58 words
A video signal processing system according to claim 1, wherein the video signal processing system further comprises an analog-to-digital converter for converting the input video signals from analog signals to digital signals, and outputting to the processing circuit, and a digital-to-analog converter for converting the video signals read out from the memory from digital signals to analog signals.
Claim 5
Dependent Claim
49 words
A video signal processing system according to claim 1, wherein the video signal processing system further comprises a first low-pass filter for passing the low-frequency components of input video signals, and a second low-pass filter for eliminating unnecessary high-frequency components of the video signals read out from the memory.
Claim 6
Dependent Claim
36 words
A video signal processing system according to claim 1, wherein the video signal processing system further comprises a generating circuit for generating clock pulses for storing and reading out video signals to and from the memory.
References Cited (Backward Citations)
US3584235A
Cited
US3700797A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-07 | 1993-11-06 | 1994-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-07 | 1997-11-06 | 1998-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-07 | 2001-11-06 | 2002-05-08 | $7700.00 | Window Closed / Lapsed |