US4929917A
Expired / Lapsed
US
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Phase-locked loop circuit
Assignee: Pioneer Corp
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Filing: 1988-12-22
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Granted: 1990-05-29
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Expires: 2008-12-22
Abstract
Abstract A phase-locked loop circuit (PLL) to which a phase-synchronization signal is intermittently supplied, both of the natural angular frequency of the PLL and the damping factor of the same are so determined as to prevent a phase difference produced at the next sampling point from exceeding the linear property range of a phase comparator even when the extraneous electrical disturbance enters the PLL. In addition, when the level of a clock control signal supplied to a variable frequency oscillator which varies the clock signal of the PLL in phase and frequency exceeds a predetermined value, the level of the clock control signal is limited to the predetermined value. As a result, it is possible to prevent the output signal of the phase difference from having any discontinuity.
Inventors
- 👤 Fumihiko Yokogawa
- 👤 Ryuichi Naito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:24
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; H03L7/093; G11B7/00; G11B7/004; G11B7/005
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
140 words
A recording medium drive apparatus which drives a recording medium on which clock marks are recorded to produce a read signal having a period which may vary about a clock period T s , comprising: a phase-locked loop (PLL) circuit for producing a clock signal comprising: phase comparator means having a linear characteristic range of ±α, wherein said phase comparator means produces a clock control signal having a magnitude which varies depending upon a phase difference between the clock signal and the read signal; and variable frequency oscillator means for generating the clock signal so that the frequency of said clock signal varies in response to the magnitude of said clock control signal; wherein the following relation stands: |ω.sub.n ·ζ|≦|α/2π·T.sub.s | where ω 2 and ζ are the natural angular frequency and the damping factor of the PLL loop, respectively.
Claim 2
Dependent Claim
140 words
A recording medium drive apparatus which drives a recording medium on which clock marks are recorded to produce a read signal having a period which may vary about a clock period T s , comprising: a phase-locked loop (PLL) circuit for producing a clock signal comprising: phase comparator means having a linear characteristic range of ±α, wherein said phase comparator means produces a clock control signal having a magnitude which varies depending upon a phase difference between the clock signal and the read signal; and variable frequency oscillator means for generating the clock signal so that the frequency of said clock signal varies in response to the magnitude of said clock control signal; wherein the following relation stands: |ω.sub.n ·ζ|≦|α/2π·T.sub.s | where ω 2 and ζ are the natural angular frequency and the damping factor of the PLL loop, respectively.
Claim 3
Dependent Claim
56 words
The recording medium drive apparatus as set forth in claim 1, wherein said clock signal serves as a data reading clock signal in a data signal receiving circuit with a data signal reading window of a window width of an angular range β, and wherein the following relations stand: β≦α; and |ω.sub.n ·ζ|≦|K·β/2π.multidot.T.sub.s | wherein 0<K<1.
Claim 4
Dependent Claim
128 words
A recording medium drive apparatus which drives a recording medium on which clock marks are recorded to produce a read signal having a period which may vary about a clock period T s , comprising: a phase-locked loop (PLL) circuit for producing a clock signal comprising: phase comparator means having a linear characteristic range, wherein said phase comparator means produces a clock control signal having a magnitude which varies depending upon a phase difference between the clock signal and the read signal; variable frequency oscillator means for generating the clock signal so that the frequency of said clock signal varies in response to the magnitude of said clock control signal; and level limiter means for preventing the magnitude of said clock control signal from exceeding a predetermined value.
Claim 5
Dependent Claim
128 words
A recording medium drive apparatus which drives a recording medium on which clock marks are recorded to produce a read signal having a period which may vary about a clock period T s , comprising: a phase-locked loop (PLL) circuit for producing a clock signal comprising: phase comparator means having a linear characteristic range, wherein said phase comparator means produces a clock control signal having a magnitude which varies depending upon a phase difference between the clock signal and the read signal; variable frequency oscillator means for generating the clock signal so that the frequency of said clock signal varies in response to the magnitude of said clock control signal; and level limiter means for preventing the magnitude of said clock control signal from exceeding a predetermined value.
Claim 6
Dependent Claim
21 words
The recording medium drive apparatus as set forth in claim 3, wherein said level limiter means comprises an amplitude limiter means.
Claim 7
Dependent Claim
191 words
A recording medium drive apparatus which drives a recording medium on which clock marks are recorded to produce a read signal having a period which may vary about a clock period T s , comprising: a phase-locked loop (PLL) circuit for producing a clock signal comprising: phase comparator means having a linear characteristic range, wherein said phase comparator means produces a clock control signal having a magnitude which varies depending upon a phase difference between the clock signal and the read signal; variable frequency oscillator means for generating the clock signal so that the frequency of said clock signal varies in response to the magnitude of said clock control signal; and level limiter means for preventing the magnitude of said clock control signal from exceeding a predetermined value; wherein said level limiter means comprises: sample and hold means for sampling the magnitude of said clock control signal at a predetermined sampling frequency to produce a sample value; and level control means for decreasing the magnitude of said clock control signal when the magnitude of said clock control signal reaches a value larger than said sample value by a predetermined reference amount.
Claim 8
Dependent Claim
191 words
A recording medium drive apparatus which drives a recording medium on which clock marks are recorded to produce a read signal having a period which may vary about a clock period T s , comprising: a phase-locked loop (PLL) circuit for producing a clock signal comprising: phase comparator means having a linear characteristic range, wherein said phase comparator means produces a clock control signal having a magnitude which varies depending upon a phase difference between the clock signal and the read signal; variable frequency oscillator means for generating the clock signal so that the frequency of said clock signal varies in response to the magnitude of said clock control signal; and level limiter means for preventing the magnitude of said clock control signal from exceeding a predetermined value; wherein said level limiter means comprises: sample and hold means for sampling the magnitude of said clock control signal at a predetermined sampling frequency to produce a sample value; and level control means for decreasing the magnitude of said clock control signal when the magnitude of said clock control signal reaches a value larger than said sample value by a predetermined reference amount.
References Cited (Backward Citations)
US4617527A
Cited
US4596963A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-28 | 1993-11-27 | 1994-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-28 | 1997-11-27 | 1998-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-28 | 2001-11-27 | 2002-05-29 | $7700.00 | Window Closed / Lapsed |