Communication adapter for store loop communication system

Claim 2

A single chip adapter for interfacing a data processing terminal with a loop communications system comprising: a plurality of control registers operable for storing data and/or control information; a control interface means operable for selecting a first one of the control registers; an internal data bus and control lines interconnecting the control registers and the interface means; a transmit circuit means operable for processing information for dispatching on said loop system; a receive circuit means operable for processing information received from said loop communications system and for setting selected bits in a second one of the control registers; and an internal modem interface control logic means operable for monitoring said first and second one of the registers and utilizing bit settings in said registers for generating electrical signals for enabling/disabling the transmit circuit means and/or the receive circuit means so that data is being received and/or is being transmitted on said loop.

Claim 3

The adapter of claim 1 further including an off chip microcomputer; an external data bus coupling the control interface means and the microcomputer; said data bus being operable for carrying data; and a plurality of control lines connecting the control interface means and the microcomputer and operable for conveying control information between said microcomputer and the control interface means.

Claim 4

The adapter of claim 2 further including: first means interconnecting the transmit circuit means to the loop and operable for converting from a first polarity to a second polarity the electrical signals outputted from the transmit circuit means; and second means coupled to the receive circuit means and operable for converting from the second polarity to the first polarity electrical signals extracted from the loop communications system.

Claim 5

The adapter of claim 2 further including means operable for monitoring a predetermined bit in said first one of the control registers and operable for generating an enabling signal when the bit is placed in a first state; and means coupled to the receive circuit means and responsive to the enabling signal for extracting a data stream from said loop communications system simultaneously sending the data stream to the off-chip microcomputer and returning said data stream to said loop communications system with the electrical characteristics of said data stream being unchanged.

Claim 6

The adapter of claim 1 further including means operable for monitoring at least one predetermined bit in said first one of the control registers and operable for enabling the terminal to operate in a first mode if the bit is set to a first state and operable to operate in a second mode if the bit is set to a second state.

Claim 7

The adapter of claim 5 wherein the first mode represents a primary mode wherein the adapter and attached station provide the supervisory functions on said loop.

Claim 8

The adapter of claim 5 wherein the second mode represents a secondary mode wherein the adapter with attached station provides non-supervisory functions.

Claim 9

The adapter of claim 1 wherein the plurality of control registers includes a set of write registers operable to receive data from the control interface means; and a set of read registers operable to receive data from the internal modem interface means.

Claim 10

The adapter of claim 1 wherein the transmit circuit means includes a transmit clock and control logic means operable for generating a transmit clock; and a transmit combinatorial logic circuitry operable to utilize the transmit clock to selectively transmit a stream of data supplied to the adapter from the data processing terminal.

Claim 11

The adapter of claim 9 wherein the transmit clock and control logic means includes a phase lock loop.

Claim 12

The adapter of claim 1 wherein the receive circuit means includes a receive clock and control logic means operable for generating a receive clock; a receive latch; and receive combinatorial logic circuitry operable to utilize the receive clock to Clock Data into the receive latch.

Claim 13

A single chip circuit arrangement operable for interfacing a data processing device with a loop communications system comprising: a plurality of write registers; a plurality of read registers; a plurality of simplex lines operable for carrying control information; a bidirectional data bus operable for transporting data into and away from said single chip circuit arrangement; first interface decoding means coupled to the data bus and the simplex lines and operable for monitoring the simplex lines and the bidirectional data bus and to select as a control register one of the plurality of registers identified by signals on said lines; second means coupled to the write registers and operable for receiving data from the write registers, processing said data for transmission on said loop communications system; third means coupled to the read registers and operable for receiving data from said loop communications system; processing the data and placing it in a read register; and fourth means operable for examining the control register and extracting information for providing electrical signals for enabling/disabling the second means and/or the third means so that data is being received and/or is being transmitted on said loop communications system.

Claim 14

A single chip circuit arrangement operable for interfacing a data processing device with a loop communications system comprising: a plurality of write registers; a plurality of read registers; a plurality of simplex lines operable for carrying control information; a bidirectional data bus operable for transporting data into and away from said single chip circuit arrangement; first interface decoding means coupled to the data bus and the simplex lines and operable for monitoring the simplex lines and the bidirectional data bus and to select as a control register one of the plurality of registers identified by signals on said lines; second means coupled to the write registers and operable for receiving data from the write registers, processing said data for transmission on said loop communications system; third means coupled to the read registers and operable for receiving data from said loop communications system; processing the data and placing it in a read register; and fourth means operable for examining the control register and extracting information for providing electrical signals for enabling/disabling the second means and/or the third means so that data is being received and/or is being transmitted on said loop communications system.

Claim 15

The circuit arrangement of claim 12 further including means coupled to the third means and operable for selectively extracting data from said loop examining the data and replacing the data on the loop without affecting the electrical characteristics of said data.

Claim 16

The circuit arrangement of claim 12 further including: a main microprocessor; a shared RAM operable for storing commands and messages generated at the main microprocessor; and a secondary microprocessor operable to access the RAM and to control the simplex lines and/or the data bus so that the circuit arrangement performs in accordance with commands being issued from said microprocessors.

Claim 17

In a loop communications network having a protocol for exchanging packets of information between terminals on said loop with said protocol having a predetermined sequence of bits for identifying special characters within said packets of information; an improved single chip adapter for connecting the terminals to the loop communications network comprising: a read data register for receiving data from said loop communications network; a write data register for receiving data from one of the terminals; a plurality of control registers for providing a command/status interface between the single chip adapter and said one of the terminals; a plurality of data signal lines connected to said one of the terminals; a plurality of control signal lines connected to said one of the terminals; a decoding combinatorial circuit means interconnecting the signal lines with the control registers and the read and write data registers; said decoding combinatorial circuit means being operable for monitoring the signal lines and for selecting one of the control registers identified by signals on said lines; a first circuit means coupled to the read data register and when activated causing data to be transmitted from the loop into said read data register; a second circuit means coupled to the write data register and when activated causing data to be transmitted from the write data register to the loop; and third circuit means for monitoring said one of the control register and using the electrical states of selected bits within said register for generating control signals for activating the first and/or the second circuit means.

Claim 18

In a loop communications network having a protocol for exchanging packets of information between terminals on said loop with said protocol having a predetermined sequence of bits for identifying special characters within said packets of information; an improved single chip adapter for connecting the terminals to the loop communications network comprising: a read data register for receiving data from said loop communications network; a write data register for receiving data from one of the terminals; a plurality of control registers for providing a command/status interface between the single chip adapter and said one of the terminals; a plurality of data signal lines connected to said one of the terminals; a plurality of control signal lines connected to said one of the terminals; a decoding combinatorial circuit means interconnecting the signal lines with the control registers and the read and write data registers; said decoding combinatorial circuit means being operable for monitoring the signal lines and for selecting one of the control registers identified by signals on said lines; a first circuit means coupled to the read data register and when activated causing data to be transmitted from the loop into said read data register; a second circuit means coupled to the write data register and when activated causing data to be transmitted from the write data register to the loop; and third circuit means for monitoring said one of the control register and using the electrical states of selected bits within said register for generating control signals for activating the first and/or the second circuit means.

Claim 19

The single chip adapter of claim 15 further including a serializer circuit coupling the write data register to the loop; and a deserializer circuit coupling the loop to the read data register.

Claim 20

The single chip adapter of claim 15 further including a monitor circuit means coupling the second circuit means to the loop; said monitor circuit means being responsive to a signal generated from the third circuit means and operable for extracting a data stream from the loop and returning said data stream on the loop without affecting the electrical characteristics of the data.

Claim 21

The single chip adapter of claim 15 wherein the first circuit means further includes a decoder circuit for intercepting packets of information flowing from the loop into the adapter and as predetermined sequence of bits representative of special characters are being decoded setting control bits with another of the control registers.

Claim 22

The single chip adapter set forth in claim 18 further including an interrupt logic circuit means being responsive to the setting of control bits within said another of the control registers and operable for generating an interrupt signal on an interrupt line emanating from said single chip adapter.

Claim 23

The single chip adapter set forth in claim 17 wherein the monitor circuit means includes a first D-type data latch for receiving data from the loop; a first combinatorial logic circuit means connected to the D-type data latch, said first combinatorial logic circuit means responsive to the electrical state of bits within the control registers and operable to select and pass data from the first D-type latch or data from said one of the terminals; a second D-type latch for receiving data from the first combinatorial logic circuit means; and a second combinatorial logic circuit means connected to the second D-type latch and controlled by bit settings in the control registers to pass data outputted from the second D-type latch onto the loop or to pass recently received loop data back onto the loop.