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US4939101A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making direct bonded wafers having a void free interface

Assignee: Fairchild Semiconductor Corp
•
Filing: 1988-09-06
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Granted: 1990-07-03
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Expires: 2008-09-06
📄 Original PDF 🌐 Google Patents

Abstract

Abstract Wafers which are direct bonded to each other in accordance with prior art processes suffer from voids at their bonded interface. Annealing such composite structures at high temperature and high pressure (for silicon wafers preferably about 1,100° C. and 15,000 psi) eliminates all voids which are not a result of the presence of a particle on one of the wafers at the time of mating.

Inventors

  • 👤 Robert D. Black
  • 👤 Stephen D. Arthur
  • 👤 Robert S. Gilmore
  • 👤 II Homer H. Glascock

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 16:38
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10W; H10W10/00; H10W10/10; H10W10/181; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S228/00; Y10S228/903

Claims Analysis

Total Claims: 26
Claim 1
Independent Claim 77 words
A method of thermally bonding a bonding surface of a first semiconductor wafer to a bonding surface of a second semiconductor wafer, said method comprising: cleaning said bonding surfaces; placing said bonding surfaces in contact to form a direct bond between said wafers; annealing said direct bond at an elevated temperature under a hydrostatic pressure of at least 300 psi under conditions in which the interface between said bonding surfaces is at all times free of fluids.
Claim 2
Independent Claim 77 words
A method of thermally bonding a bonding surface of a first semiconductor wafer to a bonding surface of a second semiconductor wafer, said method comprising: cleaning said bonding surfaces; placing said bonding surfaces in contact to form a direct bond between said wafers; annealing said direct bond at an elevated temperature under a hydrostatic pressure of at least 300 psi under conditions in which the interface between said bonding surfaces is at all times free of fluids.
Claim 3
Dependent Claim 15 words
The method recited in claim 1 wherein said hydrostatic pressure is at least 1,000 psi.
Claim 4
Dependent Claim 15 words
The method recited in claim 1 wherein said hydrostatic pressure is at least 10,000 psi.
Claim 5
Dependent Claim 14 words
The method recited in claim 1 wherein said hydrostatic pressure is about 15,000 psi.
Claim 6
Dependent Claim 28 words
The method recited in claim 1 wherein said bonding face of said first semiconductor wafer is silicon; and said bonding face of said second semiconductor wafer is silicon.
Claim 7
Dependent Claim 29 words
The method recited in claim 1 wherein: said bonding surface of said first semiconductor wafer is silicon; and said bonding face of said second semiconductor wafer is silicon oxide.
Claim 8
Dependent Claim 30 words
The method recited in claim 1 wherein: said bonding face of said first semiconductor wafer is silicon oxide; and said bonding face of said second semiconductor wafer is silicon oxide.
Claim 9
Dependent Claim 31 words
The method recited in claim 1 wherein the step of placing said bonding surfaces in contact is carried out in a vacuum at a pressure of less than 10 -5 Torr.
Claim 10
Dependent Claim 24 words
The method recited in claim 1 wherein the step of placing the bonding surfaces in contact is carried out in the absence of nitrogen.
Claim 11
Dependent Claim 25 words
The method recited in claim 1 wherein the step of placing said bonding surfaces in contact is carried out in an atmosphere of pure oxygen.
Claim 12
Dependent Claim 27 words
The method recited in claim 1 further comprising the step of: pre-annealing said bond at an elevated temperature at a hydrostatic pressure of less than 30 psi.
Claim 13
Independent Claim 31 words
A method of eliminating voids between direct bonded wafers comprising the steps of: providing said direct bonded wafers; and annealing said wafers at a hydrostatic pressure of at least 300 psi.
Claim 14
Independent Claim 31 words
A method of eliminating voids between direct bonded wafers comprising the steps of: providing said direct bonded wafers; and annealing said wafers at a hydrostatic pressure of at least 300 psi.
Claim 15
Dependent Claim 17 words
The method recited in claim 12 wherein said annealing step is carried out at an elevated temperature.
Claim 16
Dependent Claim 15 words
The method recited in claim 13 wherein said hydrostatic pressure is at least 1,000 psi.
Claim 17
Dependent Claim 15 words
The method recited in claim 13 wherein said hydrostatic pressure is at least 10,000 psi.
Claim 18
Dependent Claim 14 words
The method recited in claim 13 wherein said hydrostatic pressure is about 15,000 psi.
Claim 19
Independent Claim 37 words
A method of collapsing a void disposed along the bonded interface between two direct bonded wafers comprising the step of: annealing said direct bond at an elevated temperature under a hydrostatic pressure of at least 300 psi.
Claim 20
Independent Claim 37 words
A method of collapsing a void disposed along the bonded interface between two direct bonded wafers comprising the step of: annealing said direct bond at an elevated temperature under a hydrostatic pressure of at least 300 psi.
Claim 21
Dependent Claim 17 words
The method recited in claim 1 wherein: said elevated temperature is in the vicinity of 1,100° C.
Claim 22
Dependent Claim 17 words
The method recited in claim 4 wherein: said elevated temperature is in the vicinity of 1,100° C.
Claim 23
Dependent Claim 17 words
The method recited in claim 13 wherein: said elevated temperature is in the vicinity of 1,100° C.
Claim 24
Dependent Claim 17 words
The method recited in claim 16 wherein: said elevated temperature is in the vicinity of 1,100° C.
Claim 25
Dependent Claim 31 words
The method recited in claim 11 wherein: said pre-annealing step seals the edges of the bonding area of the wafer to isolate voids at the bonding interface from the ambient atmosphere.
Claim 26
Dependent Claim 17 words
The method recited in claim 1 wherein said first and second semiconductor wafers are both single crystalline.

References Cited (Backward Citations)

US3333324A Cited
EP0077881A2 Cited
EP0174010A2 Cited
US4705585A Cited
US4762269A Cited
US4818323A Cited
US4774196A Cited
US4883215A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-07-02 1994-01-01 1994-07-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-07-02 1998-01-01 1998-07-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-07-02 2002-01-01 2002-07-03 $7700.00 Window Closed / Lapsed

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