Virtual bit map processor

Claim 2

A single instruction multiple data parallel processor, comprising: an array of processing elements, including a plurality of edge processing elements along the periphery of said processing element array; memory means in each said processing element for storing a multiplicity of data value at specified address locations; said memory means collectively storing an array of data values, said array of data values comprising a multiplicity of segments, each said segment comprising a set of data values equal in size to said array of processing elements and stored at a corresponding segment address in said memory means; primary addressing means, coupled to all of said memory means, for generating a sequence of said segment addresses; said memory means including means for collectively accessing one segment of said array of data values for each said segment address generated by said primary addressing means; edge addressing means for generating a plurality of edge address values corresponding to each segment address generated by said primary addressing means, each edge address value comprising a segment address for a segment of said data array neighboring the segment of said data array corresponding to said segment address generated by said primary addressing means; and neighbor means in each said processing element for accessing data values from each of its neighboring processing elements; said neighbor means in each of said edge processing elements including edge accessing means, coupled to said edge addressing means, for accessing data values stored in one of said memory means at a location corresponding to one of said edge address values.

Claim 3

A single instruction multiple data parallel processor as set forth in claim 1, wherein said primary address means includes row address counter means for generating a sequence of binary row address values, column address counter means for generating a sequence of binary column address values, and means for combining said binary row address values and said column address values to generate said sequence of segment address values; each said binary value including a plurality of bits; said means for combining including means for reversing the order of the bits in one of said binary address values and for ORing the resulting binary value with the other one of said binary address values; whereby said segment address value has a fixed, predefined number of bits regardless of the number of rows and columns in said data array.

Claim 4

A single instruction multiple data parallel processor as set forth in claim 1, wherein each said memory means includes two data storage elements for each said segment address, including one storage element for storing an input data value and a second storage element for storing a computed data value computed by said processing element; whereby input data values are accessible by said edge accessing means even after computed data values have been stored by said processing elements in said memory means.

Claim 5

A single instruction multiple data parallel processor as set forth in claim 1, said memory means of each said edge processing element including two memory banks, said data values stored in said memory means of said edge processing elements being stored so that data values in neighboring ones of said segments are stored in different ones of said two memory banks; each said edge processing means including means for accessing a data value in one of said two memory banks at a location corresponding to said segment address generated by said primary address means, said edge accessing means in each said edge processing means including means for accessing a data value in the other one of said two memory banks at a location corresponding to one of said edge address values.

Claim 6

In a single instruction multiple data parallel processor, having an array of processing elements, including a plurality of processing elements along the periphery of said processing element array, and a set of memory means including memory means in each said processing element for storing a multiplicity of data values at specified address locations; a method of processing an array of data larger than said array of processing elements, the steps of the method comprising: storing an array of data values in said set of memory means, said array of data values comprising a multiplicity of segments, each said segment comprising a set of data values equal in size to said array of processing elements and stored at a corresponding segment address in said set of memory means; generating a sequence of said segment addresses and sending said segment addresses to said set of memory means for collectively accessing one segment of said array of data values for each said generated segment address; generating a plurality of edge address values corresponding to each segment address generated by said primary addressing means, each edge address value comprising a segment address for a segment of said data array neighboring the segment of said data array corresponding to said segment address generated by said primary addressing means; and accessing neighboring data values for each said processing elements, said accessing step including the step of accessing, for each of said processing elements along the periphery of said processing element array, data values stored in one of said memory means at a location corresponding to one of said edge address values.

Claim 7

In a single instruction multiple data parallel processor, having an array of processing elements, including a plurality of processing elements along the periphery of said processing element array, and a set of memory means including memory means in each said processing element for storing a multiplicity of data values at specified address locations; a method of processing an array of data larger than said array of processing elements, the steps of the method comprising: storing an array of data values in said set of memory means, said array of data values comprising a multiplicity of segments, each said segment comprising a set of data values equal in size to said array of processing elements and stored at a corresponding segment address in said set of memory means; generating a sequence of said segment addresses and sending said segment addresses to said set of memory means for collectively accessing one segment of said array of data values for each said generated segment address; generating a plurality of edge address values corresponding to each segment address generated by said primary addressing means, each edge address value comprising a segment address for a segment of said data array neighboring the segment of said data array corresponding to said segment address generated by said primary addressing means; and accessing neighboring data values for each said processing elements, said accessing step including the step of accessing, for each of said processing elements along the periphery of said processing element array, data values stored in one of said memory means at a location corresponding to one of said edge address values.

Claim 8

A method of processing an array of data as set forth in claim 5, wherein said step of generating a sequence of segment addresses includes the steps of generating a sequence of binary row address values, generating a sequence of binary column address values, and combining said binary row address values and said column address values to generate said sequence of segment address values; each said binary value including a plurality of bits; said combining step including the steps of reversing the order of the bits in one of said binary address values and ORing the resulting binary value with the other one of said binary address values; whereby said segment address value has a fixed, predefined number of bits regardless of the number of rows and columns in said data array.

Claim 9

A single instruction multiple data parallel processor, comprising: an array of processing elements, including a plurality of processing elements along the periphery of said processing element array; memory means in each said processing element for storing a multiplicity of data values at specified address locations; said memory means collectively storing an array of data values, said array of data values comprising a multiplicity of segments, each said segment comprising a set of data values equal in size to said array of processing elements and stored at a corresponding segment address in said memory means; primary addressing means, coupled to all of said memory means, for generating a sequence of said segment addresses; said memory means including means for collectively accessing one segment of said array of data values for each said segment address generated by said primary addressing means; edge addressing means for generating a plurality of edge address values corresponding to each segment address generated by said primary addressing means, each edge address value comprising a segment address for a segment of said data array neighboring the segment of said data array corresponding to said segment address generated by said primary addressing means; and neighbor means in each said processing element for accessing data values from each of its neighboring processing elements; said neighbor means in each of said processing elements along the periphery of said processing element array including means, coupled to said edge addressing means, for accessing data values stored in one of said memory means at a location corresponding to one of said edge address values.

Claim 10

A single instruction multiple data parallel processor, comprising: an array of processing elements, including a plurality of processing elements along the periphery of said processing element array; memory means in each said processing element for storing a multiplicity of data values at specified address locations; said memory means collectively storing an array of data values, said array of data values comprising a multiplicity of segments, each said segment comprising a set of data values equal in size to said array of processing elements and stored at a corresponding segment address in said memory means; primary addressing means, coupled to all of said memory means, for generating a sequence of said segment addresses; said memory means including means for collectively accessing one segment of said array of data values for each said segment address generated by said primary addressing means; edge addressing means for generating a plurality of edge address values corresponding to each segment address generated by said primary addressing means, each edge address value comprising a segment address for a segment of said data array neighboring the segment of said data array corresponding to said segment address generated by said primary addressing means; and neighbor means in each said processing element for accessing data values from each of its neighboring processing elements; said neighbor means in each of said processing elements along the periphery of said processing element array including means, coupled to said edge addressing means, for accessing data values stored in one of said memory means at a location corresponding to one of said edge address values.