US4949168A
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Decoding equalizer
Assignee: Japan Broadcasting Corp
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Filing: 1988-09-19
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Granted: 1990-08-14
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Expires: 2008-09-19
Abstract
Abstract A decoding equalizer of high definition television signal transmission mode, such as MUSE, and a subrange-type A/D converter suitable for the equalizer. The decoding equalizer samples input data in equalization at a frequency twice the sampling frequency of the trunk system, with the equalizing A/D converter operating at a lower resolution and higher speed than the A/D converter for the trunk system. The subrange-type A/D converter includes A/D converters in multiple stages, with their driving clock frequencies having a specified relationship so that they are used commonly for the A/D conversdion of the high definition television signal and the A/D conversion of a test signal for detecting the transmission characteristics.
Inventors
- 👤 Yuichi Ninomiya
- 👤 Yuichi Iwadate
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:13
CPC Classifications
H; H04; H04N; H04N9/00; H03; H03M; H03M1/00; H03M1/06; H03M1/0617; H03M1/0675; H03M1/069; H04N19/00; H04N19/50; H04N19/59; H04N5/00; H04N5/14; H04N5/21; H04N5/211; H04N7/00; H04N7/015; H04N7/0152; H04N7/12; H04N7/122; H04N7/125; H03M1/12; H03M1/14; H03M1/145
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
243 words
A decoding equalizer for a transmission system which samples a high definition television signal at a specified sampling frequency, transmits a sampled value and a test signal for detecting transmission characteristics of a transmission path, decodes the sampled value with a decoder, and equalizes the transmission characteristics of the transmission path using the test signal, the decoding equalizer comprising: first sampling means which samples the sampled value at a sampling frequency twice the specified sampling frequency said first sampling means providing an output signal; second sampling means which samples the sampled value at the specified sampling frequency, said second sampling means providing an output signal; filter means which filters the output signal of the first sampling means and produces a correction value for correcting a transmission distortion of the high definition television signal; adding means which adds a delayed version of the output signal of the second sampling means to an output signal of the filter means, said adding means providing an output signal; extracting means which extracts the test signal from the output signal of the adding means; and artithmetic means which receives data pertinent to the test signal extracted by the extracting means, calculates an error of the data with respect to predetermined reference data, determines the correction value produced by the filter means based on the calculated error, and repeats the operations of data reception, error calculation and correction value determination until the error becomes smaller than a predetermined value.
Claim 2
Dependent Claim
243 words
A decoding equalizer for a transmission system which samples a high definition television signal at a specified sampling frequency, transmits a sampled value and a test signal for detecting transmission characteristics of a transmission path, decodes the sampled value with a decoder, and equalizes the transmission characteristics of the transmission path using the test signal, the decoding equalizer comprising: first sampling means which samples the sampled value at a sampling frequency twice the specified sampling frequency said first sampling means providing an output signal; second sampling means which samples the sampled value at the specified sampling frequency, said second sampling means providing an output signal; filter means which filters the output signal of the first sampling means and produces a correction value for correcting a transmission distortion of the high definition television signal; adding means which adds a delayed version of the output signal of the second sampling means to an output signal of the filter means, said adding means providing an output signal; extracting means which extracts the test signal from the output signal of the adding means; and artithmetic means which receives data pertinent to the test signal extracted by the extracting means, calculates an error of the data with respect to predetermined reference data, determines the correction value produced by the filter means based on the calculated error, and repeats the operations of data reception, error calculation and correction value determination until the error becomes smaller than a predetermined value.
Claim 3
Dependent Claim
30 words
A decoding equalizer according to claim 1, wherein the second sampling means is formed as a sumsampling circuit and is located at a following stage of the first sampling means.
Claim 4
Dependent Claim
20 words
A decoding equalizer according to claim 1, wherein the first sampling means and the second sampling means are in parallel.
Claim 5
Dependent Claim
20 words
A decoding equalizer according to claim 1, wherein the filter means produces a correction value exclusive of a d.c. component.
Claim 6
Dependent Claim
38 words
A decoding equalizer according to claim 1, wherein the second sampling means and the filter means are supplied with sampled value data of the same resolution, said filter means neglecting a low-order bit of the sampled value data.
Claim 7
Dependent Claim
39 words
A decoding equalizer according to claim 1, wherein the filter means is supplied by the first sampling means with data, which is lower in resolution than data supplied to the second sampling means produced by a fast A/D converter.
Claim 8
Dependent Claim
37 words
A decoding equalizer according to claim 1, wherein the test signal is a reference impulse signal and the correction value produced by the filter means is produced such that the reference impulse signal has predetermined ideal characteristics.
Claim 9
Dependent Claim
32 words
A decoding equalizer according to claim 1, wherein an output signal of the filter means is made to be zero during a period when the arithmetic means is determining the correction value.
Claim 10
Dependent Claim
47 words
A decoding equalizer according to claim 1, wherein the filter means comprises first and second sets of filter means, which are used alternately by switching, such that while the first set of filter means perform a filtering operation, the second set of filter means implements data loading.
Claim 11
Dependent Claim
31 words
A decoding equalizer according to claim 1, wherein an equalizing operation by the decoder does not take place when an iteration flag indicates that equalization by the encoder is being executed.
Claim 12
Dependent Claim
106 words
A subrange-type decoder equalizing A/D converter for a transmission system which samples a television signal at a specified sampling frequency, transmits a sampled value and a test signal for detecting transmission characteristics of a transmission path, decodes the sampled value with a decoder, and equalizes the transmission characteristics of the transmission path using the test signal, wherein the subrange-type decoder equalizing A/D converter is a multi-stage subrange-type decoder equalizing converter comprising fore-stage and back-stage A/D converters connected sequentially in a plurality of stages, the fore-stage A/D converter having a driving clock frequency which is a multiple of a driving clock frequency of the back-stage A/D converter.
Claim 13
Dependent Claim
106 words
A subrange-type decoder equalizing A/D converter for a transmission system which samples a television signal at a specified sampling frequency, transmits a sampled value and a test signal for detecting transmission characteristics of a transmission path, decodes the sampled value with a decoder, and equalizes the transmission characteristics of the transmission path using the test signal, wherein the subrange-type decoder equalizing A/D converter is a multi-stage subrange-type decoder equalizing converter comprising fore-stage and back-stage A/D converters connected sequentially in a plurality of stages, the fore-stage A/D converter having a driving clock frequency which is a multiple of a driving clock frequency of the back-stage A/D converter.
Claim 14
Dependent Claim
22 words
A subrange-type decoder equalizing A/D converter according to claim 11, wherein the multi-stage subrange-type decoder equalizing A/D converter consists of two stages.
Claim 15
Dependent Claim
34 words
A subrange-type decoder equalizing A/D converter according to claim 12, wherein the fore-stage A/D converter has a 32.4 MHz driving clock frequency and the back-stage A/D converter has a 16.2 MHz driving clock frequency.
Claim 16
Dependent Claim
42 words
A subrange-type decoder equalizing A/D converter according to claim 11, wherein the back-stage A/d converter is provided with a resolution in excess of a theoretically required minimum resolution, the resolution in excess being used for correcting a total conversion output digital value.
Claim 17
Dependent Claim
24 words
A subrange-type decoder equalizing A/D converter according to claim 11, wherein the multi-stage subrange-type decoder equalizing A/D converter consists of more than two stages.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-13 | 1994-02-12 | 1994-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-13 | 1998-02-12 | 1998-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-13 | 2002-02-12 | 2002-08-14 | $7700.00 | Window Closed / Lapsed |