Method of forming a three dimensional integrated circuit structure

Claim 7

A method as set forth in claim 3, further including forming recesses in said first semiconductor substrate opening onto said one major surface thereof to define the boundaries of bridge areas of semiconductor material; and vertically flexing said plurality of elevated portions having said surface areas of electrically conductive material in the bridge areas of semiconductor material relative to said first semiconductor substrate sufficiently to accommodate registering contact with said at least some of said plurality of electrically conductive bonding pads on said second semiconductor substrate, thereby compensating for any non-level regions of said other major surface of said second semiconductor substrate.

Claim 8

A method as set forth in claim 3, wherein the application of an orientation dependent etch to said one major surface of said first semiconductor substrate forms a plurality of holes extending between said first and second major surfaces thereof; and applying an electrically conductive coating from one major surface of said first semiconductor substrate through each of said holes to the opposite other major surface of said first semiconductor substrate to provide electrical continuity between said first and second major surfaces of said first semiconductor substrate.

Claim 9

A method as set forth in claim 3, wherein at least said first semiconductor substrate is formed of (110) silicon material, and the application of an orientation dependent etch at the (110) plane thereof defines a plurality of vertically extending elevated portions from said one major surface of said first semiconductor substrate.

Claim 10

A method as set forth in claim 3, wherein a plurality of elevated portions are formed upon one major surface of each of a plurality of semiconductor substrates, including said second seminconductor substrate, by applying an orientation dependent etch to said one major surface of each of said plurality of semiconductor substrates; applying a coating of electrically conductive material to the surface area of each of said elevated portions formed on said one major surface of each of said plurality of semiconductor substrates; forming a plurality of electrically conductive bonding pads on the other major surface of each of said plurality of semiconductor substrates, including said first semiconductor substrate; arranging said plurality of semiconductor substrates in stacked juxtaposition with each other to dispose said one major surface of each of said semiconductor substrates in opposing registration with said other major surface of the semiconductor substrate adjacent thereto; providing circuit function-performing areas on respective major surfaces of said semiconductor substrates; and interconnecting the circuit function-performing areas of said stacked juxtaposed plurality of semiconductor substrates by forming contacts between at least some of said plurality of electrically conductive bonding pads on each of said semiconductor substrates and the surface areas having the coating of electrically conductive material on said elevated portions of the semiconductor substrate adjacent thereto.