US4956569A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS logic circuit for high voltage operation
Assignee: STMicroelectronics SRL
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Filing: 1989-06-30
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Granted: 1990-09-11
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Expires: 2009-06-30
Abstract
Abstract A CMOS logic circuit for converting a low voltage logic signal with a range O-VCC into a high voltage logic signal with a range O-VPP, which may be entirely made with enhancement-type transistors, comprises an additional p-channel, decoupling transistor functionally connected in series with the p-channel transistor of the CMOS circuit which is connected to the high voltage node VPP and the additional decoupling transistor is driven by a bias voltage tied to the VPP voltage and lower than the latter by a certain preset value. The so-called gated breakdown of p-channel transistors is effectively prevented and furthermore these circuits, destined to operate under a high supply voltage, may be fabricated through a normal CMOS fabrication process not requiring particular fabrication techniques for the p-channel transistors subject to gated breakdown conditions or the formation of depletion-type transistors and without the use of special circuits which require oscillator generated driving signals.
Inventors
- 👤 Marco Olivo
- 👤 Luigi Pascucci
- 👤 Carlo Riva
- 👤 Paolo Rosini
- 👤 Corrado Villa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:00
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00315; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/3565
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
215 words
A CMOS logic circuit employing solely enhancement-type transistors and comprising at least a network formed by a first p-channel transistor and a second n-channel transistor functionally connected in electrical series between a high voltage supply VPP, on which a VPP voltage gradually develops in an asymptotic way starting from a minimum value equal to a supply voltage VCC following a transition of the circuit and during a period subsequent thereto, and a ground rail of the circuit, an output node between said series-connected transistors on which producing a high voltage logic signal having a range between zero and VPP and which is a replica of a low voltage logic signal, having a range between zero and VCC, applied to the gates connected in common of said first and second transistors, and characterized by comprising means for preventing a gated breakdown of said p-channel transistor constituted substantially by a third p-channel transistor, functionally connected between said first p-channel transistor and said intermediate output node, said third p-channel transistor having a gate which is forced to ground potential when said VPP voltage maintains itself equal to said VCC voltage and which is biased at a voltage lower than said VPP voltage by a constant preset value when said VPP voltage rises to an asymptotic maximum value thereof.
Claim 2
Dependent Claim
215 words
A CMOS logic circuit employing solely enhancement-type transistors and comprising at least a network formed by a first p-channel transistor and a second n-channel transistor functionally connected in electrical series between a high voltage supply VPP, on which a VPP voltage gradually develops in an asymptotic way starting from a minimum value equal to a supply voltage VCC following a transition of the circuit and during a period subsequent thereto, and a ground rail of the circuit, an output node between said series-connected transistors on which producing a high voltage logic signal having a range between zero and VPP and which is a replica of a low voltage logic signal, having a range between zero and VCC, applied to the gates connected in common of said first and second transistors, and characterized by comprising means for preventing a gated breakdown of said p-channel transistor constituted substantially by a third p-channel transistor, functionally connected between said first p-channel transistor and said intermediate output node, said third p-channel transistor having a gate which is forced to ground potential when said VPP voltage maintains itself equal to said VCC voltage and which is biased at a voltage lower than said VPP voltage by a constant preset value when said VPP voltage rises to an asymptotic maximum value thereof.
Claim 3
Dependent Claim
33 words
A circuit according to claim 1, wherein the gate of said third p-channel transistor is connected to said high voltage node VPP through a bias network which comprises a series of diode-connected transistors.
Claim 4
Dependent Claim
13 words
A circuit according to claim 1, wherein said logic circuit is an inverter.
Claim 5
Dependent Claim
13 words
A circuit according to claim 1, wherein said logic circuit is a latch.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-10 | 1994-03-12 | 1994-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-10 | 1998-03-12 | 1998-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-10 | 2002-03-12 | 2002-09-11 | $7700.00 | Window Closed / Lapsed |