Circuit arrangement for processing sampled analogue electrical signals

Claim 2

A circuit arrangement for processing samples analog electrical current signals comprising: means for combining, in predetermined proportions, an input sample current in a present sample period with current derived from input sample current in one or more preceding sample periods, and means for deriving a processed output signal from the combined current produced by the combining means in successive sample periods; wherein the circuit arrangement further comprises a plurality of circuit modules, each circuit module having a current input for receiving a bidirectional input signal current and a current output for supplying a bidirectional output signal current, means for adding a bias current to the bidirectional input signal current to produce a unidirectional current for processing by the circuit module, and means for subtracting a suitably scaled bias current from a processed unidirectional current to produce a bidirectional signal current at the current output of the circuit module.

Claim 3

A circuit arrangement as claimed in claim 1 wherein one of the circuit modules comprises a current memory module which is capable of reproducing at its output in one sampling period a scaled version of a current applied to its input in a previous sampling period.

Claim 4

A circuit arrangement as claimed in claim 2 wherein the current memory module comprises a current input, a current output, first and second switches controlled by first and second non-overlapping clock signals, and first and second memory cells, wherein the current input is coupled to the first memory cell by means of the first switch and the first memory cell is coupled to the second memory cell by means of the second switch, an output of the second memory cell being coupled to the current output of the current memory module.

Claim 5

A circuit arrangement as claimed in claim 3, wherein each memory cell comprises a field effect transistor having a capacitor connected between its gate and source electrodes.

Claim 6

A circuit arrangement as claimed in claim 4 wherein which in each memory cell the field effect transistor forms an output branch of a current mirror circuit.

Claim 7

A circuit arrangement, as claimed in claim 5, in wherein the first and second switches are connected so as to isolate the input and output branches of each current mirror circuit, the output branch of a first current mirror circuit being connected to an input branch of a second current mirror.

Claim 8

A circuit arrangement as claimed in claim 5 or claim 6, wherein at least one current mirror circuit has a non-unity current ratio between its input and output branches.

Claim 9

A circuit arrangement as claimed in claim 6 wherein the second current mirror circuit has a plurality of output branches.

Claim 10

A circuit arrangement as claimed in claim 2 wherein the current memory module includes a first memory cell having an input, an output, means comprising a first switch which is conductive during a first portion of a sample period for connecting the input of the first memory cell to a main current conducting path of a transistor, means comprising a second switch which is conductive during the first portion for connecting a junction of the first switch and the main current conducting path of the transistor to a current maintaining means, and means for connecting the main current conducting path of the transistor to the output of the first memory cell during a second portion of the sampling period, a second memory cell having an input coupled to the output of the first memory cell and an output coupled to the output of the current memory module, and means for coupling the input of the current memory module to the input of the first memory cell.

Claim 11

A circuit arrangement as claimed in claim 9 wherein the means for connecting the main current conducting path of the transistor to the output of the first memory cell comprises a third switch which is conductive during a second portion of the sampling period which does not overlap the first portion, an output current from the first memory cell being available when the third switch is conductive.

Claim 12

A circuit arrangement as claimed in claim 10 wherein the second memory cell comprises an input, an output, means comprising a first switch which is conductive during a second portion of a sample period for connecting the input of the second memory cell to the main current conducting path of a second transistor, means comprising a second switch which is conductive during the second portion for connecting a junction of the first switch and the main current conducting path of the second transistor to a current maintaining means, and means comprising a third switch which is conductive during a first portion of the sampling period which does not overlap the second portion for connecting the main current conducting path of the second transistor to the output of the second memory cell, an output current from the current memory module being available when the third switch of the second memory cell is conductive.

Claim 13

A circuit arrangement as claimed in any of claim 9 to 11 wherein at least one comprises a field effect transistor and the current maintaining means comprises a capacitor connected between the gate and source electrodes of the transistor.

Claim 14

A circuit arrangement as claimed in claim 12 wherein the capacitor comprises the gate-source capacitance of the transistor.

Claim 15

A circuit arrangement as claimed in any of claims 9 to 11 further comprising means for feeding a bias current to the input of the first memory cell, means for drawing a corresponding bias current from the output of the second memory cell, and a third memory cell, said third memory cell being connected in the current memory module so as to store the bias current fed into the input of the first memory cell for subtraction from the output current provided by the second memory cell.

Claim 16

A circuit arrangement as claimed in any of the claims 9 to 11 wherein the second memory cell has one or more further outputs.

Claim 17

A circuit arrangement as claim in any of claims 3 to 6 or 9-11 wherein the means for subtracting a suitably scaled bias current comprises a bias current source connected to the input of a current mirror circuit having a number of outputs corresponding to the number of outputs of the current memory module, output current(s) produced by the current mirror circuit being subtracted from the corresponding output current(s) of the second memory cell.

Claim 18

A circuit arrangement as claimed in any of claims 2 to 6 or 9-11 wherein, current memory module has differential inputs and outputs and comprises a plurality of current memory cells, means for coupling each of the differential inputs to a respective current memory cell and means for combining the outputs of selected memory cells for application to the differential current outputs.

Claim 19

A circuit arrangement as claimed in any of claims 1-4 or 9-11 including an integrator circuit module which is capable of integrating a bi-directional current applied to its input.

Claim 20

A circuit arrangement as claimed in claim 18 wherein the integrator circuit module comprises a current memory module and a feedback loop from a stored current output to a summing arrangement so that a stored current can be added to each current input sample.

Claim 21

An integrator circuit as claimed in claim 19 connected so as to integrate differential input currents.

Claim 22

A circuit arrangement as claimed in claims 1-4 further comprising a static module capable of producing at its output a scaled version of a current applied to its input.

Claim 23

A circuit arrangement as claimed in claim 21, wherein the static module has a plurality of outputs each of which is capable of producing an individually scaled output.

Claim 24

A circuit arrangement as claimed in claim 21 wherein the static module has a plurality of inputs for applying a plurality of input currents to the static module to enable current addition or subtraction to be performed by the static module.

Claim 25

A circuit arrangement as claimed in claim 23 wherein the static module performs a current inversion between its inputs and outputs.

Claim 26

A circuit arrangement as claimed in claim 21 wherein the static module comprises a current scaling circuit, the current scaling circuit comprises means for applying an input current to an input branch of a first current mirror circuit, means for applying a bias current to the input branch of the first current mirror circuit, means for feeding a current from an output branch of the first current mirror circuit to an input branch of a second current mirror circuit, means for feeding a current from an output branch of the second current mirror circuit to the output of the static module, and means for subtracting a suitably scaled bias current from the current in the output branch of the second current mirror circuit so that an output current produced by the scaling circuit is a scaled version of the input current applied to an input of the scaling circuit.

Claim 27

A circuit arrangement as claimed in claim 25, wherein the means for applying a bias current to the input branch of the first current mirror circuit comprises a first current source and means for adding the current produced by a first current source to the input current the means for subtracting a bias current comprises a second current source and a current summing junction to which an output current from the second current source and the output current from the output branch of the second current mirror are applied with appropriate polarity, and means for deriving the scaled output current from the summing junction.

Claim 28

A circuit arrangement as claimed in claim 25 wherein the second current mirror circuit has a plurality of outputs, the static module has a corresponding plurality of outputs, and each output of the second current mirror circuit is coupled to a corresponding output of the static module.

Claim 29

A circuit arrangement as claimed in claim 27 wherein the means for subtracting the suitably scaled bias current comprises a bias current source connected to an input of a further current mirror circuit having a number of outputs corresponding to the number of outputs of the second current mirror circuit, output currents produced by the further current mirror circuit being subtracted from corresponding output currents of the second current mirror circuit.

Claim 30

A circuit arrangement as claimed is claim 28 wherein the static module is connected to produce at its output an inversion of the current applied to its input, wherein the input of the static module is coupled to the input of the further current mirror circuit instead of the input of the first current mirror circuit.

Claim 31

A circuit arrangement as claimed in claim 28 wherein the static module is connected to subtract a first current from a second current and has a first input for application of the second current which is coupled to the input of the first current mirror circuit, a second input for application of the first current which is coupled to the input of the further current mirror circuit, and one or more outputs which are coupled to respective output branches of the second current mirror circuit.

Claim 32

A circuit arrangement as claim in claim 21 wherein the static module is connected to process a differential input current and produce a differential output current.

Claim 33

A circuit arrangement as claim in claim 31 wherein the static module comprises, first and second inputs for receiving a differential input current, first and second outputs for producing a differential output current, means for coupling the first input of the static module to a first input of a first current summing means, means for coupling a first bias current source to a second input of the first current summing means, means for coupling an output of the first current summing means to an input branch of a first current mirror circuit, means for coupling the second input to a first input of a second current summing means, means for coupling a second bias current source to a second input of the second current summing means, means for coupling an output of the second current summing means to an input branch of a second current mirror circuit, means for coupling a first output branch of the first current mirror circuit to an input branch of a third current mirror circuit, means for coupling a first output branch of the second current mirror circuit to an input branch of a fourth current mirror circuit, means for coupling a second output branch of the first current mirror circuit to a first input of a third current summing means, means for coupling an output branch of the fourth current mirror circuit to a second input of the third current summing means, means for coupling an output of the third current summing means to the first output, means for coupling a second branch of the second current mirror circuit to a first input of a fourth current summing means, means for coupling an output branch of the third current mirror circuit to a second input of the fourth current summing means, and means for coupling an output of the fourth current summing means to the second output.

Claim 34

A circuit arrangement as claimed in claim 32 in which the static module has a number of further differential outputs wherein each of the current mirror circuits has a corresponding number of further output branches each of which is connected to appropriate further summing means.

Claim 35

A circuit arrangement as claimed in claim 32 wherein the static module has a number of further differential inputs, each further differential input being connected to a further input of the first and second current summing means.

Claim 36

A circuit arrangement as claimed in claim 7 wherein the second current mirror circuit has a plurality of output branches.

Claim 37

A circuit arrangement as claimed in claim 14 wherein, the means for subtracting a suitably scaled bias current comprises a bias current source connected to the input of a current mirror circuit having a number of outputs corresponding to the number of outputs of the current memory module, output current(s) produced by the current mirror circuit being subtracted from corresponding output current(s) of the second memory cell.

Claim 38

A circuit arrangement as claimed in claim 7 wherein, the current memory module has differential inputs and outputs and comprises a plurality of current memory cells, means for coupling each of the differential inputs to a respective current memory cell, and means for combining the outputs of selected memory cells for application to the differential current outputs.

Claim 39

A circuit arrangement as claimed in claim 14 wherein the current memory module has differential inputs and outputs and comprises a plurality of current memory cells, emans for coupling each of the differential inputs to a respective current memory cell, and means for combining the outputs of selected memory cells for application to the differential current outputs.

Claim 40

A circuit arrangement as claimed in claim 7 including an integrator circuit module which is capable of integrating a bidirectional current applied to its input.

Claim 41

A circuit arrangement as claimed in claim 39 wherein the integrator circuit module comprises a current memory module and a feedback loop from a stored current output to a summing arrangement so that a stored current can be added to each current input sample.

Claim 42

An integrator circuit as claimed in claim 18 connected so as to integrate differential input currents.

Claim 43

A circuit arrangement as claimed in claim 22 wherein the static module has a plurality of inputs for applying a plurality of input currents to the static module to enable current addition or subtraction to be performed by the static module.

Claim 44

A circuit arrangement as claimed in claim 21 wherein the static module performs a current inversion between its inputs and outputs.

Claim 45

A circuit arrangement as claimed in claim 23 wherein the static module comprises a current scaling circuit, the current scaling circuit comprising means for applying an input current to an input branch of a first current mirror circuit, means for applying a bias current to the input branch of the first current mirror circuit, means for feeding a current from an output branch of the first current mirror circuit to an input branch of a second current mirror circuit, means for feeding a current from an output branch of the second current mirror circuit to the output of the static module, and means for subtraction a suitably scaled bias current from the current in the output branch of the second current mirror circuit so that an output current produced by the scaling circuit is a scaled version of the input current applied to an input of the scaling circuit.

Claim 46

A circuit arrangement as claimed in claim 26 wherein the second current mirror circuit has a plurality of outputs, the static module has a corresponding plurality of outputs, and each output of the second current mirror circuit is coupled to a corresponding output of the static module.

Claim 47

A circuit arrangement as claimed in claim 25 wherein the static module is connected to process a differential input current and produce a differential output current.

Claim 48

A circuit arrangement as claimed in claim 46 wherein the static module comprises, first and second inputs for receiving a differential input current, first and second outputs for producing a differential output current, means for coupling the first input of the static module to a first input of a first current summing means, means for coupling a first bias current source to a second input of the first current summing means, means for coupling an output of the first current summary means to an input branch of a first current mirror circuit, means for coupling the second input to a first input of a second current summing means, means for coupling a second bias current source to a second input of the second current summing means, means for coupling an output of the second current summing means to an input branch of a second current mirror circuit, means for coupling a first output branch of the first current mirror circuit to an input branch of a third current mirror circuit, means for coupling a first output branch of the second current mirror circuit to an input branch of a fourth current mirror circuit, means for coupling a second output branch of the first current mirror circuit to a first input of a third current summing means, means for coupling an output branch of the fourth current mirror circuit to a second input of the third current summing means, means for coupling an output of the third current summing means to the first output, means for coupling a second branch of the second current mirror circuit to a first input of a fourth current summing means, means for coupling an output branch of the third current mirror circuit to a second input of the fourth current summing means, and means for coupling an output of the fourth current summing means to the second output.