One transistor flash EPROM cell

Claim 2

An electrically programmable and erasable semiconductor device, provided on a substrate, comprising: a drain region provided in the substrate; a source region provided in the substrate, said source region comprising a first lightly doped source region and a second heavily doped source region provided in said first source region and being spaced from said drain region to define a channel region therebetween; dielectric means for limiting tunnelling during programming and allowing tunnelling during erasing, said dielectric means comprising a tunnelling dielectric having a first thickness provided on a portion of the substrate corresponding to the position of a portion of said source region and a gate oxide having a second thickness greater than said first thickness provided on a portion of the substrate corresponding to the position of a portion of said channel and a portion of said drain region; a floating gate provided on said dielectric means; an inter-gate dielectric provided on said floating gate; and a control gate provided on said inter-gate dielectric.

Claim 3

A semiconductor device according to claim 1, wherein said floating gate has a thickness of less than 1000Å and an actual doping level of less than 5×10 18 cm -3 .

Claim 4

A semiconductor device according to claim 1, wherein said floating gate has a thickness of less than 1000Å and an activated carrier concentration of less than 1×10 17 cm -3 .

Claim 5

A semiconductor device according to claim 2, wherein: said tunneling dielectric has a thickness of less than approximately 150Å; and said gate oxide has a thickness of greater than approximately 200Å.

Claim 6

A flash EPROM cell having self-limiting erase characteristics, provided on a substrate, comprising: a drain region provided in the substrate; a source region provided in the substrate and spaced from said drain region to define a channel region between said source and drain regions, said source region comprising a first lightly doped region and a second more heavily doped region provided in said first region; multi-thickness dielectric means, provided on the substrate, said multi-thickness dielectric means comprising a gate oxide for limiting tunneling during programming of the cell and providing an energy barrier to the flow of notes into the substrate, and a tunnelling dielectric for allowing tunneling during erasing of the cell; a floating gate provided on said multi-thickness dielectric means, said floating gate having a doping level sufficient only to allow injected electrons to redistribute during the programming of the EPROM cell; inter-gate dielectric means provided on said floating gate; and a control gate provided on said inter-gate dielectric means.

Claim 7

A flash EPROM cell having self-limiting erase characteristics, provided on a substrate, comprising: a drain region provided in the substrate; a source region provided in the substrate and spaced from said drain region to define a channel region between said source and drain regions, said source region comprising a first lightly doped region and a second more heavily doped region provided in said first region; multi-thickness dielectric means, provided on the substrate, said multi-thickness dielectric means comprising a gate oxide for limiting tunneling during programming of the cell and providing an energy barrier to the flow of notes into the substrate, and a tunnelling dielectric for allowing tunneling during erasing of the cell; a floating gate provided on said multi-thickness dielectric means, said floating gate having a doping level sufficient only to allow injected electrons to redistribute during the programming of the EPROM cell; inter-gate dielectric means provided on said floating gate; and a control gate provided on said inter-gate dielectric means.

Claim 8

A flash EPROM cell according to claim 5, wherein said multi-thickness dielectric includes a tunneling dielectric overlapping a portion of said source region, and a gate oxide overlapping a portion of said drain region and a portion of the channel.

Claim 9

A flash EPROM cell according to claim 6, wherein: said tunneling dielectric overlaps a portion of said first lightly doped source region and a portion of said second more heavily doped region.

Claim 10

A flash EPROM cell according to claim 7, wherein: said floating gate has a thickness of less than 1000Å and an activated carrier concentration of less than 1×10 17 cm -3 .

Claim 11

A flash EPROM cell according to claim 8, wherein: said tunneling dielectric has a thickness of less than approximately 150Å; and said gate oxide has a thickness of greater than 200Å.

Claim 12

A flash EPROM cell according to claim 6, wherein said floating gate comprises semi-insulating polysilicon.

Claim 13

A one transistor flash EPROM cell provided on a substrate, comprising: a drain region provided in the substrate; a first source region provided in the substrate, said first source region being spaced from said drain region to define a channel region therebetween; a second source region provided in said first source region, said second source region having a greater doping level than said first source region; a tunneling dielectric provided on a portion of the substrate corresponding to a first portion of said first source region and a portion of said second source region, said tunneling dielectric having a first thickness; a gate oxide provided on a portion of the substrate corresponding to a second portion of said first source region and a portion of said drain region, said gate oxide having a second thickness greater than said first thickness; a floating gate provided on portions of said tunneling dielectric and said gate oxide, said floating gate having a doping level sufficient only to allow injected electrons to redistribute during the programming of the EPROM cell; an inter-gate oxide layer provided on said floating gate; and a control gate provided on said inter-gate oxide.

Claim 14

A one transistor flash EPROM cell provided on a substrate, comprising: a drain region provided in the substrate; a first source region provided in the substrate, said first source region being spaced from said drain region to define a channel region therebetween; a second source region provided in said first source region, said second source region having a greater doping level than said first source region; a tunneling dielectric provided on a portion of the substrate corresponding to a first portion of said first source region and a portion of said second source region, said tunneling dielectric having a first thickness; a gate oxide provided on a portion of the substrate corresponding to a second portion of said first source region and a portion of said drain region, said gate oxide having a second thickness greater than said first thickness; a floating gate provided on portions of said tunneling dielectric and said gate oxide, said floating gate having a doping level sufficient only to allow injected electrons to redistribute during the programming of the EPROM cell; an inter-gate oxide layer provided on said floating gate; and a control gate provided on said inter-gate oxide.

Claim 15

A flash EPROM cell according to claim 11, wherein said gate oxide is provided on a portion of the substrate corresponding to substantially the entire channel region.

Claim 16

A semiconductor device according to claim 11, wherein said floating gate has a thickness of less than 1000Å and an activated carrier concentration of less than approximately 1×10 17 cm -3 .

Claim 17

A semiconductor device according to claim 13, wherein: said tunneling dielectric has a thickness of less than approximately 150Å; and said gate oxide has a thickness of greater than approximately 200Å.

Claim 18

A one transistor flash EPROM cell provided on a substrate, comprising: a first drain region provided in the substrate; a second drain region provided in said first drain region, said second drain region having a greater doping level than said first drain region; a first source region provided in the substrate, said first source region being spaced from said first drain region to define a channel region therebetween; a second source region provided in said first region, said second source region having a greater doping level than said first source region; a tunneling dielectric provided on the substrate, said tunneling dielectric overlapping a first portion of said first source region and a portion of said second source region; a gate oxide provided on the substrate, said gate oxide overlapping a second portion of said first source region and portions of said first and second drain regions; a semi-insulating floating gate provided on said tunneling dielectric and said gate oxide; an inter-gate oxide layer provided on said floating gate; and a control gate provided on said inter-gate oxide.

Claim 19

A one transistor flash EPROM cell provided on a substrate, comprising: a first drain region provided in the substrate; a second drain region provided in said first drain region, said second drain region having a greater doping level than said first drain region; a first source region provided in the substrate, said first source region being spaced from said first drain region to define a channel region therebetween; a second source region provided in said first region, said second source region having a greater doping level than said first source region; a tunneling dielectric provided on the substrate, said tunneling dielectric overlapping a first portion of said first source region and a portion of said second source region; a gate oxide provided on the substrate, said gate oxide overlapping a second portion of said first source region and portions of said first and second drain regions; a semi-insulating floating gate provided on said tunneling dielectric and said gate oxide; an inter-gate oxide layer provided on said floating gate; and a control gate provided on said inter-gate oxide.

Claim 20

A flash EPROM cell according to claim 15, wherein said gate oxide is provided on a portion of the substrate corresponding to substantially the entire channel region.

Claim 21

A semiconductor device according to claim 15, wherein said floating gate has a thickness of less than 1000Å and an actual doping level of less than 5×10 18 cm -3 .

Claim 22

A semiconductor device according to claim 15, wherein said floating gate has a thickness of less than 1000Å and an activated carrier concentration of less than approximately 1×10 17 cm -3 .

Claim 23

A semiconductor device according to claim 17, wherein: said tunneling dielectric has a thickness of less than approximately 150Å; and said gate oxide has a thickness of greater than approximately 200Å.

Claim 24

A one transistor flash EPROM cell provided on a p-type substrate, comprising: an n - -type drain region provided in the substrate; an n + -type drain region provided in said n - -type drain region; an n - -type source region provided in the substrate, said n - -type source region being spaced from said n - -type drain region to define a channel region therebetween; an n + -type source region provided in said n - -type source region; a tunneling oxide provided on the substrate, corresponding to a first portion of said n - -type source region and a portion of said n + -type source region, said tunneling oxide having a thickness of less than approximately 150Å; a gate oxide provided on a portion of the substrate, corresponding to a second portion of said n - -type source region and portions of said n - -type and n + -type drain regions, the overlap of said gate oxide and said n - -type source providing an energy barrier to the flow of holes into the substrate, said gate oxide having a thickness of greater than approximately 200Å; a semi-insulating polysilicon floating gate provided on said tunneling oxide and said gate oxide, said floating gate having a thickness of less than 1000Å and an activated carrier concentration of less than approximately 1×10 17 cm -3 ; an inter-gate oxide layer provided on said floating gate; and a control gate provided on said inter-gate oxide.

Claim 25

A one transistor flash EPROM cell provided on a p-type substrate, comprising: an n - -type drain region provided in the substrate; an n + -type drain region provided in said n - -type drain region; an n - -type source region provided in the substrate, said n - -type source region being spaced from said n - -type drain region to define a channel region therebetween; an n + -type source region provided in said n - -type source region; a tunneling oxide provided on the substrate, corresponding to a first portion of said n - -type source region and a portion of said n + -type source region, said tunneling oxide having a thickness of less than approximately 150Å; a gate oxide provided on a portion of the substrate, corresponding to a second portion of said n - -type source region and portions of said n - -type and n + -type drain regions, the overlap of said gate oxide and said n - -type source providing an energy barrier to the flow of holes into the substrate, said gate oxide having a thickness of greater than approximately 200Å; a semi-insulating polysilicon floating gate provided on said tunneling oxide and said gate oxide, said floating gate having a thickness of less than 1000Å and an activated carrier concentration of less than approximately 1×10 17 cm -3 ; an inter-gate oxide layer provided on said floating gate; and a control gate provided on said inter-gate oxide.

Claim 26

An improved transistor, including a substrate, a drain region provided in the substrate, a first source region provided in the substrate, the first source region being spaced from the drain region to define a channel region therebetween, a second source region provided in the first region, the second source region having a greater doping level than the first source region, an dielectric layer provided on the substrate, a floating gate provided on the dielectric layer, an inter-gate oxide layer provided on the floating gate, and a control gate provided on the inter-gate oxide, characterized in that: the dielectric layer comprises: a tunneling oxide overlapping a portion of the first source region and a portion of the second source region, and a gate oxide overlapping a portion of the drain region; and the floating gate has a thickness of less than 1000Å and an activated carrier concentration of less than 1×10 17 cm -3 .

Claim 27

An improved transistor, including a substrate, a drain region provided in the substrate, a first source region provided in the substrate, the first source region being spaced from the drain region to define a channel region therebetween, a second source region provided in the first region, the second source region having a greater doping level than the first source region, an dielectric layer provided on the substrate, a floating gate provided on the dielectric layer, an inter-gate oxide layer provided on the floating gate, and a control gate provided on the inter-gate oxide, characterized in that: the dielectric layer comprises: a tunneling oxide overlapping a portion of the first source region and a portion of the second source region, and a gate oxide overlapping a portion of the drain region; and the floating gate has a thickness of less than 1000Å and an activated carrier concentration of less than 1×10 17 cm -3 .

Claim 28

An improved transistor according to claim 21, further characterized in that the tunneling oxide overlaps a first portion of the first source region and the gate oxide overlaps a second portion of the first source region.

Claim 29

An electrically programmable and erasable semiconductor device, provided on a substrate, comprising: a drain region provided in the substrate; a source region provided in the substrate, said source region being spaced from said drain region to define a channel region therebetween; a dielectric overlying said channel and portions of said source region and said drain regions; a floating gate provided on said dielectric means, said floating gate having a thickness of less than 1000Å and an actual doping level of less than 5×10 18 cm -3 ; an inter-gate dielectric provided on said floating gate; and a control gate provided on said inter-gate dielectric.

Claim 30

An electrically programmable and erasable semiconductor device, provided on a substrate, comprising: a drain region provided in the substrate; a source region provided in the substrate, said source region being spaced from said drain region to define a channel region therebetween; a dielectric overlying said channel and portions of said source region and said drain regions; a floating gate provided on said dielectric means, said floating gate having a thickness of less than 1000Å and an actual doping level of less than 5×10 18 cm -3 ; an inter-gate dielectric provided on said floating gate; and a control gate provided on said inter-gate dielectric.

Claim 31

An electrically programmable and erasable semiconductor device according to claim 23, wherein said dielectric comprises a tunnelling dielectric having a thickness less than approximately 150Å overlying a portion of said source region and a portion of said channel, and a gate oxide having a thickness greater than approximately 200Å overlying a portion of said channel and a portion of said drain region.

Claim 32

An electrically programmable and erasable semiconductor device according to claim 24, wherein said source region comprises a first lightly doped source region and a second heavily doped source region provided in said first source region.

Claim 33

An electrically programmable and erasable semiconductor device according to claim 23, wherein said floating gate has an activated carrier concentration of less than 1×10 17 cm -3 .

Claim 34

An electrically programmable and erasable semiconductor device according to claim 25, wherein said tunnelling dielectric overlies a portion of said first source region and a portion of said second source region, and said gate oxide overlies a portion of said first source region, said channel and a portion of said drain region.