Computer hardware executive

Claim 2

In a computer system including a host computer processor connected to a host computer memory via a host memory bus, the improvement comprising computer hardware executive means connected to said memory bus for implementing executive functions in said computer system, said computer hardware executive means comprising: memory mapped interface means for providing a connection between said memory bus and said computer hardware executive; microsequence control logic means coupled to said memory mapped interface means for enabling programmable control of said computer hardware executive and containing a set of operation algorithms based on a set of parameters; associative memory logic means coupled to said microsequence control logic means for storing entries in computer executive tables and for retrieving, sorting, making comparisons against and modifying the entries in the computer executive tables as directed by the microsequence control logic means; and register logic means coupled to the microsequence control logic means for storing, retrieving and modifying the parameters of the operation algorithms as directed by the microsequence control logic means.

Claim 3

The improvement of claim 1 wherein the computer hardware executive includes a plurality of memory locations, each having associated therewith one of a range of memory location addresses and wherein said memory mapped interface means comprises: address space detector means coupled to the host memory bus for determining if an address provided by the host processor is in the range of addresses; executive function detector means coupled to the host memory bus for determining whether an address in the range of addresses is dedicated to an executive function; host processor address interface means coupled to said host memory bus for maintaining addresses provided by the host processor; host processor write data interface means coupled to the host memory bus for maintaining data provided by the host processor; host processor read data interface means coupled to the host memory bus for returning data to the host processor; host processor read/write signal interface means coupled to the host memory bus for determining whether the host processor is requesting a read function from or a write function to the computer hardware executive means; host processor data ready logic means coupled to the host memory bus for informing the host computer when data from the computer hardware executive is ready for transfer to the host processor; host processor busy logic means coupled to inform the host computer when it no longer needs to maintain connection to the memory mapped interface means; host processor interrupt logic means coupled to the host processor to inform the host processor to execute alternative processing; host processor reset signal interface means coupled to determine when the host processor is being initialized; and host processor request signal interface means coupled to determine when the host processor has furnished valid information to the memory mapped interface means.

Claim 4

The improvement of claim 2 wherein the address space detector means comprises: a comparator network.

Claim 5

The improvement of claim 2 wherein the executive function detector means comprises: a comparator network.

Claim 6

The improvement of claim 2 wherein the host processor address interface means comprises: a buffer network.

Claim 7

The improvement of claim 2 wherein the host processor write data interface means comprises: a buffer network.

Claim 8

The improvement of claim 2 wherein the host processor read data interface means comprises: a buffer network.

Claim 9

The improvement of claim 2 wherein the host processor read/write signal interface means comprises: a buffer network.

Claim 10

The improvement of claim 2 wherein the host processor data ready logic means comprises: a buffer network.

Claim 11

The improvement of claim 2 wherein the host processor busy logic means comprises: a first flip-flop network (206) coupled to the output of the host processor request signal interface means; a second flip-flop network (208) coupled to the first flip-flop network; an AND/OR invert network coupled to the first and second flip-flop networks; a third flip-flop network coupled to the output of the AND/OR invert network; and a buffer network (105) connected to the output of the third flip-flop network.

Claim 12

The improvement of claim 2 wherein the host processor interrupt logic means comprises: a buffer network.

Claim 13

The improvement of claim 2 wherein the host processor reset signal interface means comprises: a buffer network (111).

Claim 14

The improvement of claim 2 wherein the host processor request signal interface means comprises: a buffer network (101) having an output connected to the input of the host processor busy logic means.

Claim 15

The improvement of claim 1 wherein the microsequence control logic means comprises: microprogram memory means (104) for enabling retrieving of a microprogram; microinstruction register means (108) coupled to the microprogram memory means for holding a microprogram received from the microprogram memory means; microinstruction address transform means (106) coupled to the microprogram memory means for generating a distinct address corresponding to each distinct microinstruction; command logic means (118, 120) coupled to the microinstruction address transform means for supplying the microinstruction address transform means with a set of unique function identifying signals; and microinstruction decode logic means coupled to the output of the microinstruction register means for generating a set of control signals in response to the output of the microinstruction register means.

Claim 16

The improvement of claim 14 wherein the microinstruction register means comprises: a register including a plurality of flip-flop networks, each flip-flop network being dedicated to a distinct bit of the microinstruction.

Claim 17

The improvement of claim 14 wherein the microinstruction address transform means comprises: a plurality of AND/OR invert gates connected to the output of the command logic means.

Claim 18

The improvement of claim 1 wherein the associative memory logic means comprises a plurality of associative memory logic banks interconnected by an associative memory bus structure each of the associative memory logic banks comprising: a random access memory; an arithmetic unit (36) connected to the output of the random access memory; a data multiplexer (38) connected to an input of the random access memory; a plurality of location capture flip-flop networks (40) connected to an input of the random access memory; a logic gate (44) having a first input connected to the output of the plurality of location capture flip-flop networks and having a second input connected to the output of the arithmetic unit; a location capture multiplexer having its input connected to the output of the logic gate and having an output connected to input of the plurality of location capture flip-flop networks; a buffer network (48) for alternately connecting or disconnecting the outputs of each of the plurality of location capture flip-flop networks to the associative memory bus structure; and an AND gate (46) connected to the output of the logic gate (44).

Claim 19

The improvement of claim 17 wherein the associative memory logic means further comprises: bank selection logic network means (52) for selectively activating one or more of the plurality of associative memory logic banks, each associative memory logic bank having a plurality of storage locations and bit selection logic means (54) for selectively activating one or more of the plurality of storage locations in the selected associative memory logic bank.

Claim 20

The improvement of claim 18 wherein the register logic means further comprises: exchange register means for storing an intermediate value in the same word format as that used by the host processor; a queue counter; priority register means for storing simultaneously the output of the bank selection logic network means and the output of the bit selection logic means; a time counter; a multiplexer connected to the exchange register, the queue counter, the priority register and the time counter; and omit generation logic means connected to the queue counter and time counter for selecting a bit to be used as a data bit common to each of the plurality of storage locations.

Claim 21

The improvement of claim 2 wherein the microsequence control logic means comprises: microprogram memory means (104) for enabling retrieving of a microprogram; microinstruction register means (108) coupled to the microprogram memory means for holding a microprogram received from the microprogram memory means; microinstruction address transform means (106) coupled to the microprogram memory means for generating a distinct address corresponding to each distinct microinstruction; command logic means (118, 120) coupled to the microinstruction address transform means for supplying the microinstruction address transform means with a set of unique function identifying signals; and microinstruction decode logic means coupled to the output of the microinstruction register means for generating a set of control signals in response to the output of the microinstruction register means.

Claim 22

The improvement of claim 20 wherein the associative memory logic means comprises a plurality of associative memory logic banks interconnected by an associative memory bus structure each of the associative memory logic banks comprising: a random access memory; an arithmetic unit (36) connected to the output of the random access memory; a data multiplexer (38) connected to an input of the random access memory; a plurality of location capture flip-flop networks (40) connected to an input of the random access memory; a logic gate (44) having a first input connected to the output of the plurality of location capture flip-flop networks and having a second input connected to the output of the arithmetic unit; a location capture multiplexer having its input connected to the output of the logic gate and having an output connected to input of the plurality of location capture flip-flop networks; a buffer network (48) for alternately connecting or disconnecting the outputs of each of the plurality of location capture flip-flop networks to the associative memory bus structure; and an AND gate (46) connected to the output of the logic gate (44).

Claim 23

The improvement of claim 21 wherein the associative memory logic means further comprises: bank selection logic network means (52) for selectively activating one or more of the plurality of associative memory logic banks, each associative memory logic bank having a plurality of storage locations and bit selection logic means (54) for selectively activating one or more of the plurality of storage locations in the selected associative memory logic bank.

Claim 24

The improvement of claim 21 wherein the register logic means further comprises: exchange register means for storing an intermediate value in the same word format as that used by the host processor; a queue counter; priority register means for storing simultaneously the output of the bank selection logic network means and the output of the bit selection logic means; a time counter; a multiplexer connected to the exchange register, the queue counter, the priority register and the time counter; and omit generation logic means connected to the queue counter and time counter for selecting a bit to be used as a data bit common to each of the plurality of storage locations.