US4965722A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic memory refresh circuit with a flexible refresh delay dynamic memory
Assignee: NEC Electronics Corp
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Filing: 1989-11-27
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Granted: 1990-10-23
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Expires: 2009-11-27
Abstract
Abstract A microprocessor includes an execution unit executing a program according to an instruction, an instruction prefetch circuit storing a plurality of instructions to be executed by the execution unit, a refresh control circuit controlling a refresh operation of a dynamic memory coupled to an external bus and a control unit. The control unit receives bus access request signals from the execution unit and from the instruction prefetch circuit, respectively, and a refresh request signal from the refresh control circuit and sends a refresh grant signal to the refresh control circuit in response to the refresh request signal when both the bus access request signals are absent. The refresh control circuit generates a first refresh request signal and a second refresh request signal. The control unit generates the refresh grant signal in response to the first refresh request signal only when both the bus access request signals from the execution unit and the instruction prefetch circuit are absent, but generates the refresh grant signal at any time the second refresh request signal is generated. The refresh operation is performed at least once and a counter is decremented when the refresh is granted in response to the first refresh request signal and the refresh operation is performed a plurality of times with equivalent decrementing of the counter when the refresh is granted in response to the second refresh request signal.
Inventors
- 👤 Takahiro Tokuume
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:57
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
346 words
A microprocessor coupled to a dynamic memory via an external bus, comprising an execution unit executing an instruction and generating a bus request signal to access said external bus when a data transmission is required in the execution of the instruction, a refresh timer for generating a refresh timing signal at predetermined time intervals, first means coupled to said refresh timer for generating a first refresh request signal in response to said refresh timing signal, second means coupled to said external bus for executing a refresh operation for said dynamic memory in response to a refresh grant signal supplied thereto, third means coupled to said second means for generating a refresh operation execution signal each time one refresh operation for said dynamic memory is executed, a counter coupled to said refresh timer and said third means for counting up a value thereof each time said refresh timing signal is generated and counting down the value thereof each time said refresh operation execution signal is generated, fourth means coupled to said counter for generating a second refresh request signal when the count value of said counter reaches a predetermined value, and a bus arbiter coupled to said execution unit and said first and fourth means for receiving said bus request signal and said first and second refresh request signals, said bus arbiter disregarding said first refresh request signal when said bus request signal is supplied thereto, accepting said first refresh request signal when said bus request signal is absent to generate and supply said refresh grant signal to said second means, and responding to said second refresh request signal to generate and supply said refresh grant signal to said second means irrespective of the presence of said bus request signal, said second means performing said refresh operation for said dynamic memory at least once when said refresh grant signal is generated in response to said first refresh request signal and performing said refresh operation for said dynamic memory a plurality of times when said refresh grant signal is generated in response to said second refresh request signal.
Claim 2
Dependent Claim
346 words
A microprocessor coupled to a dynamic memory via an external bus, comprising an execution unit executing an instruction and generating a bus request signal to access said external bus when a data transmission is required in the execution of the instruction, a refresh timer for generating a refresh timing signal at predetermined time intervals, first means coupled to said refresh timer for generating a first refresh request signal in response to said refresh timing signal, second means coupled to said external bus for executing a refresh operation for said dynamic memory in response to a refresh grant signal supplied thereto, third means coupled to said second means for generating a refresh operation execution signal each time one refresh operation for said dynamic memory is executed, a counter coupled to said refresh timer and said third means for counting up a value thereof each time said refresh timing signal is generated and counting down the value thereof each time said refresh operation execution signal is generated, fourth means coupled to said counter for generating a second refresh request signal when the count value of said counter reaches a predetermined value, and a bus arbiter coupled to said execution unit and said first and fourth means for receiving said bus request signal and said first and second refresh request signals, said bus arbiter disregarding said first refresh request signal when said bus request signal is supplied thereto, accepting said first refresh request signal when said bus request signal is absent to generate and supply said refresh grant signal to said second means, and responding to said second refresh request signal to generate and supply said refresh grant signal to said second means irrespective of the presence of said bus request signal, said second means performing said refresh operation for said dynamic memory at least once when said refresh grant signal is generated in response to said first refresh request signal and performing said refresh operation for said dynamic memory a plurality of times when said refresh grant signal is generated in response to said second refresh request signal.
Claim 3
Dependent Claim
466 words
A microprocessor coupled via an external bus to a dynamic memory, comprising an instruction prefetch unit temporarily storing at least one instruction and generating a first bus request signal to access said external bus when an instruction to be prefetched is required, an execution unit executing an instruction from said instruction prefetch unit and generating a second bus request signal to access said external bus when a data transmission is required in the execution of the instruction, a bus arbiter coupled to said instruction prefetch unit and said execution unit for receiving said first and second bus request signals, said bus arbiter accepting said second bus request signal irrespective of the presence of said first bus request signal to allow a bus access for said data transmission and accepting said first bus request signal when said second bus request signal is absent to allow a bus access for the instruction prefetch, a refresh timer for generating a refresh timing signal at predetermined time intervals, first means coupled to said refresh timer for generating a first refresh request signal in response to said refresh timing signal, second means coupled to said external bus for executing a refresh operation for said dynamic memory in response to a refresh grant signal supplied thereto, third means coupled to said second means for generating a refresh operation execution signal each time one refresh operation for said dynamic memory is executed, a counter coupled to said refresh timer and said third means for counting up a value thereof each time said refresh timing signal is generated and counting down the value thereof each time said refresh operation execution signal is generated, and fourth means coupled to said counter for generating a second refresh request signal when the count value of said counter reaches a predetermined value, said bus arbiter being further coupled to said first and fourth means to receive said first and second refresh request signals, said bus arbiter disregarding said first refresh request signal when at least one of said first and second bus request signals are supplied thereto, accepting said first refresh request signal when both of said first and second bus request signals are absent to generate and supply said refresh grant signal to said second means, and responding to said second refresh request signal to generate and supply said refresh grant signal to said second means irrespective of the presence of both of said first and second bus request signals, said second means performing said refresh operation for said dynamic memory at least once when said refresh grant signal is generated in response to said first refresh request signal and performing said refresh operation for said dynamic memory a plurality of times when said refresh grant signal is generated in response to said second refresh request signal.
Claim 4
Dependent Claim
466 words
A microprocessor coupled via an external bus to a dynamic memory, comprising an instruction prefetch unit temporarily storing at least one instruction and generating a first bus request signal to access said external bus when an instruction to be prefetched is required, an execution unit executing an instruction from said instruction prefetch unit and generating a second bus request signal to access said external bus when a data transmission is required in the execution of the instruction, a bus arbiter coupled to said instruction prefetch unit and said execution unit for receiving said first and second bus request signals, said bus arbiter accepting said second bus request signal irrespective of the presence of said first bus request signal to allow a bus access for said data transmission and accepting said first bus request signal when said second bus request signal is absent to allow a bus access for the instruction prefetch, a refresh timer for generating a refresh timing signal at predetermined time intervals, first means coupled to said refresh timer for generating a first refresh request signal in response to said refresh timing signal, second means coupled to said external bus for executing a refresh operation for said dynamic memory in response to a refresh grant signal supplied thereto, third means coupled to said second means for generating a refresh operation execution signal each time one refresh operation for said dynamic memory is executed, a counter coupled to said refresh timer and said third means for counting up a value thereof each time said refresh timing signal is generated and counting down the value thereof each time said refresh operation execution signal is generated, and fourth means coupled to said counter for generating a second refresh request signal when the count value of said counter reaches a predetermined value, said bus arbiter being further coupled to said first and fourth means to receive said first and second refresh request signals, said bus arbiter disregarding said first refresh request signal when at least one of said first and second bus request signals are supplied thereto, accepting said first refresh request signal when both of said first and second bus request signals are absent to generate and supply said refresh grant signal to said second means, and responding to said second refresh request signal to generate and supply said refresh grant signal to said second means irrespective of the presence of both of said first and second bus request signals, said second means performing said refresh operation for said dynamic memory at least once when said refresh grant signal is generated in response to said first refresh request signal and performing said refresh operation for said dynamic memory a plurality of times when said refresh grant signal is generated in response to said second refresh request signal.
References Cited (Backward Citations)
US4535330A
Cited
US4625301A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |