Associative memory having simplified memory cell circuitry

Claim 2

An associative memory including at least one memory cell which can be accessed for reading, writing and coincidence detection, said associative memory comprising: first and second bit lines connected to said memory cell, a word line connected to said memory cell, command means for generating a command signal for commanding said coincidence detection, a command line connected between said command means and said memory cell for transmitting the command signal generated by said command means to said memory cell, and a match line connected to said memory cell adapting from said memory cell for outputting from said memory cell a signal indicating the result of coincidence detection, said memory cell including, data holding means connected to said first bit line responsive to the signal on said word line for holding the data signal on said first bit line, a first switching device connected between said match line and a predetermined first potential, first control means connected to said first bit line responsive to the command signal supplied by said command line for controlling said first switching device, and second control means connected to said second bit line responsive to the data signal held in said data holding means for controlling said first switching device.

Claim 3

The associative memory according to claim 1 wherein said first switching device includes a control electrode, said first control means include a second switching device having a control electrode and connected between said first bit line and the control electrode of said first switching device, said second switching device has its control electrode connected to said command line, and said second control means includes a third switching device having a control electrode and connected between said second bit line and the control electrode of said first switching device, said third switching device having its control electrode connected to said data holding means, said memory cell further including a first capacity means connected between the control electrode of said first switching device and said first potential.

Claim 4

The associative memory according to claim 1, wherein the command signal generated by said command means includes pulse signal includes a pulse signal having a predetermined pulse width.

Claim 5

The associative memory according to claim 2, wherein said data holding means includes a fourth switching device having a control electrode and connected between said first bit line and the control electrode of said third switching device, said fourth switching device having its control electrode connected to said word line, and a second capacity means connected between the control electrode of said third switching device and said first potential.

Claim 6

The associative memory according to claim 4, wherein said first to fourth switching device each include first to fourth field effect devices of one conductivity type each having a gate electrode.

Claim 7

The associative memory according to claim 4, wherein said first capacity means include a first gate capacity formed between the gate electrode of said first field effect device and said first potential, and said second capacity means includes a second gate capacity formed between the gate electrode of said third field effect device and said first potential.

Claim 8

The associative memory according to claim 4, wherein said one conductivity type include a N type, and said first potential includes a ground potential.

Claim 9

An associative memory including at least one memory cell which can be accessed for reading, writing and coincidence detection, said associative memory comprising: first and second bit lines connected to said memory cell, a word line connected to said memory cell, command means for generating a command signal for commanding said coincidence detection, a command line connected between said command means and said memory cells for transmitting said command signal generated by said command means to said memory cell, and a coincidence detection line connected to said memory cell for outputting from said memory cells a signal showing the results of coincidence detection, said memory cell including first and second field effect transistors of one conductivity type each having a gate electrode connected in series between said first bit line and second bit line, said first field effect transistor having its gate electrode connected to said command line, said second field effect transistor having a first gate capacity formed between the gate electrode of said second field effect transistor and a predetermined first potential, a third field effect transistor having a gate electrode connected between said first bit line and the gate electrode of said second field effect transistor, said third field effect transistor having its gate electrode connected to said word line, and a fourth field effect transistor having a gate electrode connected between said coincidence detection line and said first potential, said fourth field effect transistor having its gate electrode connected to a connection node between said first and second field effect transistors, said fourth field effect transistor having a second gate capacity formed between the gate electrode of said fourth field effect transistor and said first potential.

Claim 10

An associative memory including at least one memory cell which can be accessed for reading, writing and coincidence detection, said associative memory comprising: first and second bit lines connected to said memory cell, a word line connected to said memory cell, command means for generating a command signal for commanding said coincidence detection, a command line connected between said command means and said memory cells for transmitting said command signal generated by said command means to said memory cell, and a coincidence detection line connected to said memory cell for outputting from said memory cells a signal showing the results of coincidence detection, said memory cell including first and second field effect transistors of one conductivity type each having a gate electrode connected in series between said first bit line and second bit line, said first field effect transistor having its gate electrode connected to said command line, said second field effect transistor having a first gate capacity formed between the gate electrode of said second field effect transistor and a predetermined first potential, a third field effect transistor having a gate electrode connected between said first bit line and the gate electrode of said second field effect transistor, said third field effect transistor having its gate electrode connected to said word line, and a fourth field effect transistor having a gate electrode connected between said coincidence detection line and said first potential, said fourth field effect transistor having its gate electrode connected to a connection node between said first and second field effect transistors, said fourth field effect transistor having a second gate capacity formed between the gate electrode of said fourth field effect transistor and said first potential.

Claim 11

The associative memory according to claim 8, wherein said one conductivity type includes a N type, and said first potential includes a ground potential.