Flash erasable and programmable nonvolatile semiconductor memory

Claim 1

A nonvolatile semiconductor memory comprising: a semiconductor region of a first conductivity type; and a plurality of memory cell groups, each having four memory cells, including: a shared source conductive layer of a second conductivity type formed on said semiconductor region and connected to a first potential, first, second, third and fourth drain conductive layers, of the second conductivity type, formed on said semiconductor region around said shared source conductive layer at equal distances from a center portion thereof, said first and second drain conductive layers being positioned in a first direction from said shared source conductive layer, said third and fourth drain conductive layers being positioned in a second direction, opposite to said first direction, from said shared source conductive layer, and regions between said shared source conductive layer and said first, second, third and fourth drain conductive layers constituting first, second third and fourth channel regions, respectively; first and second control gate conductive layers, extending in a third direction substantially perpendicular to said first direction, formed above said semiconductor region such that said first control gate conductive layer covers said first and second channel regions and said second control gate conductive layer covers said third and fourth channel regions, with an insulating film being sandwiched between said first and second control gate conductive layers and their respective channel regions; first, second third and fourth floating gate conductive layers respectively formed above said first, second, third and fourth channel regions in said insulating film, first, second, third and fourth erase gate electrodes respectively formed in said insulating film such that portions of said first, second, third and fourth erase gate electrodes respectively overlap portions of said first, second, third and fourth floating gate conductive layers. first and second erase gate lines extending parallel to each other, said first erase gate line being provided on one side of said four memory cells and said second erase gate line being provided on an opposite side of said four memory cells, each of said first and second erase gate lines being formed integrally with two of said first, second, third and fourth erase gate electrodes such that said first and second erase gate lines do not overlap said shared source conductive layer; and a first data line connected to said first and second drain conductive layers and a second data line connected to said third and fourth drain conductive layers.