US4970442A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Correction circuit used in horizontal deflection circuit for the correction of image distortion
Assignee: Toshiba Corp
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Filing: 1990-02-21
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Granted: 1990-11-13
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Expires: 2010-02-21
Abstract
Abstract A correction circuit is used with a horizontal deflection circuit, for the correction of an image distortion. The correction circuit comprises a line memory for sequentially fetching and storing one-field digital image data. The digital image data read out of the line memory is supplied to a D/A conversion circuit. This D/A conversion circuit converts the digital image data into an analog signal used for making a beam scan rate constant on the entire screen of a CRT. The data transfer rate used in both the line memory and the D/A conversion circuit is varied, with a clock supply rate adjusted by a frequency modulation circuit and an A/D conversion circuit on the basis of clock rate data.
Inventors
- 👤 Naohiko Harada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:07
CPC Classifications
G; G09; G09G; G09G1/00; H; H04; H04N; H04N3/00; H04N3/10; H04N3/16; H04N3/22; H04N3/23; H04N3/233; H04N3/2335
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
133 words
A correction circuit used with a horizontal deflection circuit for the correction of an image distortion, comprising: memory means for sequentially fetching and storing one-field digital image data; D/A conversion means, supplied with the one-field digital image data from the memory means, for converting the digital image data into an analog signal used for making the beam scan rate constant on a screen of a cathode ray tube; adjusting means, connected to both the memory means and the D/A conversion means, for adjusting a clock supply rate, so as to make image data transfer rate variable in both the memory means and the D/A conversion means; and clock rate data-generation means for generating clock rate data which is supplied through the adjusting means to both the memory means and the D/A conversion means.
Claim 2
Dependent Claim
133 words
A correction circuit used with a horizontal deflection circuit for the correction of an image distortion, comprising: memory means for sequentially fetching and storing one-field digital image data; D/A conversion means, supplied with the one-field digital image data from the memory means, for converting the digital image data into an analog signal used for making the beam scan rate constant on a screen of a cathode ray tube; adjusting means, connected to both the memory means and the D/A conversion means, for adjusting a clock supply rate, so as to make image data transfer rate variable in both the memory means and the D/A conversion means; and clock rate data-generation means for generating clock rate data which is supplied through the adjusting means to both the memory means and the D/A conversion means.
Claim 3
Dependent Claim
21 words
A correction circuit according to claim 1, wherein said memory means includes a line memory for storing the digital image data.
Claim 4
Dependent Claim
69 words
A correction circuit according to claim 1, wherein said adjusting means includes: frequency modulation means, supplied with the clock rate data, for modulating the frequency of a carrier wave signal generated by a carrier wave generator; and A/D conversion means for converting the carrier wave signal, whose frequency is modulated by the frequency modulating means, into a digital signal and for supplying the digital signal to the memory means.
Claim 5
Dependent Claim
46 words
A correction circuit according to claim 1, wherein said clock rate data-generation means includes: a reference clock generator; and an address signal generator, supplied with a clock by the reference clock generator, for generating an address signal to be stored in a clock rate data memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-12 | 1994-05-14 | 1994-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-12 | 1998-05-14 | 1998-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-12 | 2002-05-14 | 2002-11-13 | $7700.00 | Window Closed / Lapsed |