US4975384A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Erasable electrically programmable read only memory cell using trench edge tunnelling
Assignee: Texas Instruments Inc
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Filing: 1988-07-11
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Granted: 1990-12-04
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Expires: 2008-07-11
Abstract
Abstract An electrically programmable read only memory cell formed in a face of a semiconductor substrate which includes a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in the substrate. The trench has bottom corners sufficiently sharp so as to enhance the likelihood of tunnelling between corner regions of the trench and the floating gate over that between planar surface regions of the trench and floating gate.
Inventors
- 👤 David A. Baglee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
122 words
A method of forming an electrically programmable read only memory cell on a semiconductor substrate, comprising: forming a moat region of a first conductivity type in said substrate; etching a trench through said moat region; conformally depositing a pair of polysilicon layers over said trench and a portion of said substrate insulated from each other and said substrate by a selected thickness of insulator material; wherein said polysilicon layers form a floating gate and a control gate for said floating gate transistor and bottom corners of said trench are sufficiently sharp such that tunnelling between a corner region of said trench and said floating gate is enhanced over the likelihood of tunnelling between planar regions of said trench and said floating gate.
Claim 2
Independent Claim
122 words
A method of forming an electrically programmable read only memory cell on a semiconductor substrate, comprising: forming a moat region of a first conductivity type in said substrate; etching a trench through said moat region; conformally depositing a pair of polysilicon layers over said trench and a portion of said substrate insulated from each other and said substrate by a selected thickness of insulator material; wherein said polysilicon layers form a floating gate and a control gate for said floating gate transistor and bottom corners of said trench are sufficiently sharp such that tunnelling between a corner region of said trench and said floating gate is enhanced over the likelihood of tunnelling between planar regions of said trench and said floating gate.
Claim 3
Dependent Claim
30 words
A method according to claim 1, wherein said polysilicon layers form a floating gate and control gate for a tunnel transistor coupled to a source of said floating gate transistor.
Claim 4
Dependent Claim
19 words
A method according to claim 2, including forming a selection transistor coupled in series with said floating gate transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-03 | 1994-06-04 | 1994-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-03 | 1998-06-04 | 1998-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-03 | 2002-06-04 | 2002-12-04 | $7700.00 | Window Closed / Lapsed |