Method of detecting the width of lightly doped drain regions

Claim 1

A method of fabricating, in a substrate, a field effect transistor including lightly-doped drain regions having a selected width, comprising the steps of: (a) forming a pair of reference structures separated by a distance of twice the selected width on the substrate and forming a gate structure on the substrate, the two reference structures having substantially parallel edges defining a test region having a length and width; (b) concurrently implanting lightly-doped drain regions self-aligned with the ends of the gate structure and implanting a dopant in the test area using a first implant dosage; (c) forming spacers extending laterally from the ends of the gate structure and from the reference structures; (d) optically determining that the spacers have the selected width by detecting that the spacers fill the region between the reference structures; (e) concurrently implanting source and drain regions self-aligned with the spacers in selected portions of the lightly-doped regions and implanting a dopant in the test area using the spacers as masks using a second implant dosage greater than the first implant dosage; (f) electrically detecting the width of the spacers, by: (i) measuring the sheet resistance R sN - of the substrate de to the first implant dosage, (ii) measuring the sheet resistance R sN + of the substrate due to the combination of the first and second implant dosages, (iii) measuring the resistance R of the test region, and (iv) calculating the width of the spacers and thus the lightly-doped drain regions based upon the measured resistance values; and (g) characteristics the electrical performance of the field effect transistor based on the width of the spacers detected in said step (f).

Claim 2

A method of fabricating, in a substrate, a field effect transistor including lightly-doped drain regions having a selected width, comprising the steps of: (a) forming a pair of reference structures separated by a distance of twice the selected width on the substrate and forming a gate structure on the substrate, the two reference structures having substantially parallel edges defining a test region having a length and width; (b) concurrently implanting lightly-doped drain regions self-aligned with the ends of the gate structure and implanting a dopant in the test area using a first implant dosage; (c) forming spacers extending laterally from the ends of the gate structure and from the reference structures; (d) optically determining that the spacers have the selected width by detecting that the spacers fill the region between the reference structures; (e) concurrently implanting source and drain regions self-aligned with the spacers in selected portions of the lightly-doped regions and implanting a dopant in the test area using the spacers as masks using a second implant dosage greater than the first implant dosage; (f) electrically detecting the width of the spacers, by: (i) measuring the sheet resistance R sN - of the substrate de to the first implant dosage, (ii) measuring the sheet resistance R sN + of the substrate due to the combination of the first and second implant dosages, (iii) measuring the resistance R of the test region, and (iv) calculating the width of the spacers and thus the lightly-doped drain regions based upon the measured resistance values; and (g) characteristics the electrical performance of the field effect transistor based on the width of the spacers detected in said step (f).

Claim 9

A method of fabricating, in a substrate, a field effect transistor having lightly-doped drain regions a selected width, comprising the steps of: (a) forming a pair of reference structures on the substrate to define a test region having a width W and a length L between the reference structures and forming a gate structure on the substrate; (b) concurrently implanting lightly-doped drain regions self-aligned with the ends of the gate structure and implanting a dopant in the test area using a first implant dosage; (c) forming spacers laterally extending a width X from the ends of the gate structure and from the reference structures; (d) concurrently implanting source and drain regions self-aligned with the spacers in selected portions of the lightly-doped regions and implanting a dopant in the test area using the spacers as masks using a second implant dosage greater than the first implant dosage; (e) electrically detecting the width X of the spacers, by: (i) measuring the sheet resistance R sN - of the substrate due to the first implant dosage, (ii) measuring the sheet resistance R sN + of the substrate due to the combination of the first and second implant dosages, (iii) measuring the resistance R of the test region, and (iv) calculating the width X of the spacers in accordance with the relationship ##EQU4## where ΔCD is the measured variation in the width of the test region; and (f) characterizing the electrical performance of the field effect transistor based on the width of the spacers detected in said step (e).

Claim 10

A method of fabricating, in a substrate, a field effect transistor having lightly-doped drain regions a selected width, comprising the steps of: (a) forming a pair of reference structures on the substrate to define a test region having a width W and a length L between the reference structures and forming a gate structure on the substrate; (b) concurrently implanting lightly-doped drain regions self-aligned with the ends of the gate structure and implanting a dopant in the test area using a first implant dosage; (c) forming spacers laterally extending a width X from the ends of the gate structure and from the reference structures; (d) concurrently implanting source and drain regions self-aligned with the spacers in selected portions of the lightly-doped regions and implanting a dopant in the test area using the spacers as masks using a second implant dosage greater than the first implant dosage; (e) electrically detecting the width X of the spacers, by: (i) measuring the sheet resistance R sN - of the substrate due to the first implant dosage, (ii) measuring the sheet resistance R sN + of the substrate due to the combination of the first and second implant dosages, (iii) measuring the resistance R of the test region, and (iv) calculating the width X of the spacers in accordance with the relationship ##EQU4## where ΔCD is the measured variation in the width of the test region; and (f) characterizing the electrical performance of the field effect transistor based on the width of the spacers detected in said step (e).

Claim 11

A method of fabricating, in a substrate, a field effect transistor including lightly-doped drain regions having a selected width, in a first fabrication run, comprising the steps of: (a) providing a first pair of reference structures separated by a reference structure distance of approximately twice the selected width on the substrate, and a second pair of reference structures having substantially parallel edges defining a test region having a length and width; (b) providing a gate structure on the substrate; (c) concurrently implanting lightly-doped drain regions self-aligned with the ends of the gate structure and implanting a dopant in the test area using a first implant dosage; (d) forming spacers extending laterally from the ends of the gate structure and from each of the reference structures; (e) optically determining that the spacers have a width approximately one half of the distance between the first pair of reference structures by detecting that spacers extending from the first pair of reference structures fill the region between the first pair of reference structures; (f) concurrently implanting source and drain regions self-aligned with the spacers in selected portions of the lightly-doped regions and implanting a dopant in the test area using the spacers as masks using a second implant dosage greater than the first implant dosage; (g) electrically detecting the width of the lightly doped regions after said step (f), by: (i) measuring the sheet resistance R sN - of the substrate due to the first implant dosage, (ii) measuring the sheet resistance R sN + of the substrate due to the combination of the first and second implant dosages, (iii) measuring the resistance R of the test region, and (iv) calculating the width of the lightly-doped drain regions based upon the measured resistance values; (h) comparing the selected width and the width of the lightly-doped regions detected in said step (g) and determining an adjusted reference structure distance in accordance with the comparison; and (i) performing a second fabrication run comprising said steps (a) through (f) using the adjusted reference structure distance as the distance between the first pair of reference structures.

Claim 12

A method of fabricating, in a substrate, a field effect transistor including lightly-doped drain regions having a selected width, in a first fabrication run, comprising the steps of: (a) providing a first pair of reference structures separated by a reference structure distance of approximately twice the selected width on the substrate, and a second pair of reference structures having substantially parallel edges defining a test region having a length and width; (b) providing a gate structure on the substrate; (c) concurrently implanting lightly-doped drain regions self-aligned with the ends of the gate structure and implanting a dopant in the test area using a first implant dosage; (d) forming spacers extending laterally from the ends of the gate structure and from each of the reference structures; (e) optically determining that the spacers have a width approximately one half of the distance between the first pair of reference structures by detecting that spacers extending from the first pair of reference structures fill the region between the first pair of reference structures; (f) concurrently implanting source and drain regions self-aligned with the spacers in selected portions of the lightly-doped regions and implanting a dopant in the test area using the spacers as masks using a second implant dosage greater than the first implant dosage; (g) electrically detecting the width of the lightly doped regions after said step (f), by: (i) measuring the sheet resistance R sN - of the substrate due to the first implant dosage, (ii) measuring the sheet resistance R sN + of the substrate due to the combination of the first and second implant dosages, (iii) measuring the resistance R of the test region, and (iv) calculating the width of the lightly-doped drain regions based upon the measured resistance values; (h) comparing the selected width and the width of the lightly-doped regions detected in said step (g) and determining an adjusted reference structure distance in accordance with the comparison; and (i) performing a second fabrication run comprising said steps (a) through (f) using the adjusted reference structure distance as the distance between the first pair of reference structures.

Claim 17

A method of fabricating, in a substrate, a field effect transistor including lightly-doped drain regions having a selected width, in a first fabrication run, comprising the steps of: (a) forming a pair of reference structures on the substrate to define a test region having a width W and a length L between the reference structures and forming a gate structure on the substrate; (b) concurrently implanting lightly-doped drain regions self-aligned with the ends of the gate structure and implanting a dopant in the test area using a first implant dosage; (c) forming spacers laterally extending a width Y from the ends of the gate structure and from the reference structures; (d) concurrently implanting source and drain regions self-aligned with the spacers in selected portions of the light-doped regions and implanting a dopant in the test area using the spacers as masks using a second implant dosage greater than the first implant dosage; (e) electrically detecting the width X of the lightly-doped regions, by: (i) measuring the sheet resistance R sN - of the substrate due to the first implant dosage, (II) measuring the sheet resistance R sN + of the substrate due to the combination of the first and second implant dosages, (iii) measuring the resistance R of the test region, and (iv) calculating the width X of the lightly-doped regions in accordance with the relationship ##EQU6## where ΔCD is the measured variation in the width of the test regions; and (f) comparing the width X and the width Y to adjust the width Y for a second fabrication run.

Claim 18

A method of fabricating, in a substrate, a field effect transistor including lightly-doped drain regions having a selected width, in a first fabrication run, comprising the steps of: (a) forming a pair of reference structures on the substrate to define a test region having a width W and a length L between the reference structures and forming a gate structure on the substrate; (b) concurrently implanting lightly-doped drain regions self-aligned with the ends of the gate structure and implanting a dopant in the test area using a first implant dosage; (c) forming spacers laterally extending a width Y from the ends of the gate structure and from the reference structures; (d) concurrently implanting source and drain regions self-aligned with the spacers in selected portions of the light-doped regions and implanting a dopant in the test area using the spacers as masks using a second implant dosage greater than the first implant dosage; (e) electrically detecting the width X of the lightly-doped regions, by: (i) measuring the sheet resistance R sN - of the substrate due to the first implant dosage, (II) measuring the sheet resistance R sN + of the substrate due to the combination of the first and second implant dosages, (iii) measuring the resistance R of the test region, and (iv) calculating the width X of the lightly-doped regions in accordance with the relationship ##EQU6## where ΔCD is the measured variation in the width of the test regions; and (f) comparing the width X and the width Y to adjust the width Y for a second fabrication run.

Claim 25

A method of fabricating, in a substrate, a field effect transistor including lightly-doped drain regions having a selected width, comprising the steps of: (a) forming a pair of reference structures separated by a distance of twice the selected width on the substrate and forming a gate structure on the substrate, the two reference structures having substantially parallel edges defining a test region having a length and width; (b) concurrently implanting lightly-doped drain regions self-aligned with the ends of the gate structure and implanting a dopant in the test area using a first implant dosage; (c) forming spacers extending laterally from the ends of the gate structure and from the reference structures; (d) optically determining that the spacers have the selected width by detecting that the spacers fill the region between the reference structures; (e) concurrently implanting source and drain regions self-aligned with the spacers in selected portions of the lightly-doped regions and implanting a dopant in the test area using the spacers as masks using a second implant dosage greater than the first implant dosage; (f) electrically determining the width of the spacers, by: (i) measuring the sheet resistance R sN - of the substrate due to the first implant dosage, (ii) measuring the sheet resistance R sN + of the substrate due to the combination of the first and second implant dosages, (iii) measuring the resistance R of the test region, and (iv) calculating the width of the spacers and thus the lightly-doped drain regions based upon the measured resistance values; and (g) characterizing the reliability of the field effect transistor based on the width of the spacers determined in said step (f).

Claim 26

A method of fabricating, in a substrate, a field effect transistor including lightly-doped drain regions having a selected width, comprising the steps of: (a) forming a pair of reference structures separated by a distance of twice the selected width on the substrate and forming a gate structure on the substrate, the two reference structures having substantially parallel edges defining a test region having a length and width; (b) concurrently implanting lightly-doped drain regions self-aligned with the ends of the gate structure and implanting a dopant in the test area using a first implant dosage; (c) forming spacers extending laterally from the ends of the gate structure and from the reference structures; (d) optically determining that the spacers have the selected width by detecting that the spacers fill the region between the reference structures; (e) concurrently implanting source and drain regions self-aligned with the spacers in selected portions of the lightly-doped regions and implanting a dopant in the test area using the spacers as masks using a second implant dosage greater than the first implant dosage; (f) electrically determining the width of the spacers, by: (i) measuring the sheet resistance R sN - of the substrate due to the first implant dosage, (ii) measuring the sheet resistance R sN + of the substrate due to the combination of the first and second implant dosages, (iii) measuring the resistance R of the test region, and (iv) calculating the width of the spacers and thus the lightly-doped drain regions based upon the measured resistance values; and (g) characterizing the reliability of the field effect transistor based on the width of the spacers determined in said step (f).