US4982109A
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Circuit and method for measuring the duration of a selected pulse in a pulse train
Assignee: Sundstrand Corp
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Filing: 1989-10-04
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Granted: 1991-01-01
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Expires: 2009-10-04
Abstract
Abstract A method of measuring the duration of a selected pulse in a pulse train produces a pulse count enable logic signal in response to a start pulse to enable a first down counter to count transition points in the pulse train. The pulse count enable logic signal has a duration at least as long as two sequences of pulses in the pulse train. The first down counter counts down from a predetermined initial count representative of the selected pulse in the pulse train and enables a second counter when the count corresponding to that selected pulse is reached. The second counter is used to count high speed clock pulses until the end of the selected pulse in the pulse train. The final output count of the second counter is then used to calculate the duration of the selected pulse.
Inventors
- 👤 William J. Burwell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:30
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
195 words
A method of measuring the duration of a selected pulse in a pulse train, said method comprising the steps of: loading a first down counter with a first predetermined initial count (N); loading a second down counter with a second predetermined initial count representative of a selected pulse in an inverter drive logic signal, the duration of which is to be measured, said second counter being activated by a first predetermined output count from said first counter; loading a third down counter with a third predetermined initial count, said third counter being activated by a second predetermined output count from said second counter; supplying a series of sync pulses to said first counter, said sync pulses occurring once for each pulse sequence of said inverter drive logic signal; supplying said inverter drive logic signal to said second counter; supplying a clock signal to said third counter; supplying a start pulse to said first counter, thereby enabling said first counter to count said sync pulses; and reading the output count of said third counter after (N+1) sync pulses following said start pulse, said third counter output count being representative of the duration of said selected pulse.
Claim 2
Independent Claim
195 words
A method of measuring the duration of a selected pulse in a pulse train, said method comprising the steps of: loading a first down counter with a first predetermined initial count (N); loading a second down counter with a second predetermined initial count representative of a selected pulse in an inverter drive logic signal, the duration of which is to be measured, said second counter being activated by a first predetermined output count from said first counter; loading a third down counter with a third predetermined initial count, said third counter being activated by a second predetermined output count from said second counter; supplying a series of sync pulses to said first counter, said sync pulses occurring once for each pulse sequence of said inverter drive logic signal; supplying said inverter drive logic signal to said second counter; supplying a clock signal to said third counter; supplying a start pulse to said first counter, thereby enabling said first counter to count said sync pulses; and reading the output count of said third counter after (N+1) sync pulses following said start pulse, said third counter output count being representative of the duration of said selected pulse.
Claim 3
Dependent Claim
21 words
A method of measuring the duration of a selected pulse in a pulse train, as recited in claim 1, wherein N=2.
Claim 4
Dependent Claim
41 words
A method of measuring the duration of a selected pulse in a pulse train, as recited in claim 1, wherein said second predetermined output count equals zero and said first predetermined output count is in a range from zero to N.
Claim 5
Dependent Claim
234 words
A circuit for measuring the duration of a selected pulse in a pulse train, said circuit comprising: a first down counter for counting sync pulses, said sync pulses occurring once for each sequence of pulses in an inverter drive logic pulse train; a second down counter for counting pulses in said inverter drive logic pulse train, said second counter being activated by a first predetermined output count range from said first counter; a third down counter for counting clock pulses, said third counter being activated by a second predetermined output count from said second counter; and control means for loading said first down counter with a first predetermined initial count (N), for loading said second down counter with a second predetermined initial count representative of a selected pulse in said inverter drive logic signal, the duration of which is to be measured, for loading said third down counter with a third predetermined initial count, for supplying said sync pulses to said first counter, for supplying said inverter drive logic signal to said second counter, for supplying said clock signal to said third counter, for supplying a start pulse to said first counter, thereby enabling said first counter to count said sync pulses, and for reading the output count of said third counter after (N+1) sync pulses following said start pulse, said third counter output count being representative of the duration of said selected pulse.
Claim 6
Dependent Claim
234 words
A circuit for measuring the duration of a selected pulse in a pulse train, said circuit comprising: a first down counter for counting sync pulses, said sync pulses occurring once for each sequence of pulses in an inverter drive logic pulse train; a second down counter for counting pulses in said inverter drive logic pulse train, said second counter being activated by a first predetermined output count range from said first counter; a third down counter for counting clock pulses, said third counter being activated by a second predetermined output count from said second counter; and control means for loading said first down counter with a first predetermined initial count (N), for loading said second down counter with a second predetermined initial count representative of a selected pulse in said inverter drive logic signal, the duration of which is to be measured, for loading said third down counter with a third predetermined initial count, for supplying said sync pulses to said first counter, for supplying said inverter drive logic signal to said second counter, for supplying said clock signal to said third counter, for supplying a start pulse to said first counter, thereby enabling said first counter to count said sync pulses, and for reading the output count of said third counter after (N+1) sync pulses following said start pulse, said third counter output count being representative of the duration of said selected pulse.
Claim 7
Dependent Claim
21 words
A circuit for measuring the duration of a selected pulse in a pulse train, as recited in claim 4, wherein N=2.
Claim 8
Dependent Claim
41 words
A circuit for measuring the duration of a selected pulse in a pulse train, as recited in claim 4, wherein said second predetermined output count equals zero and said first predetermined output count is in the range of zero to two.
Claim 9
Independent Claim
172 words
A method of measuring the duration of a selected pulse in a pulse train, said method comprising the steps of: using a first counter to produce a pulse count enable logic signal pulse in response to a start pulse, said pulse count enable logic signal pulse having a duration at least as long as two sequences of pulses in an inverter drive logic signal; using a second counter to count transition points in said inverter drive logic signal, said second counter being activated by said pulse count enable logic signal pulse, and counting down from a predetermined initial count representative of a pulse in said inverter drive logic signal, the duration of which is to be measured; using a third counter to count clock pulses, said third counter being activated by a predetermined output count of said second counter; and reading the output count of said third counter after said second counter goes beyond said predetermined output count, said third counter output count being representative of the duration of said selected pulse.
Claim 10
Independent Claim
172 words
A method of measuring the duration of a selected pulse in a pulse train, said method comprising the steps of: using a first counter to produce a pulse count enable logic signal pulse in response to a start pulse, said pulse count enable logic signal pulse having a duration at least as long as two sequences of pulses in an inverter drive logic signal; using a second counter to count transition points in said inverter drive logic signal, said second counter being activated by said pulse count enable logic signal pulse, and counting down from a predetermined initial count representative of a pulse in said inverter drive logic signal, the duration of which is to be measured; using a third counter to count clock pulses, said third counter being activated by a predetermined output count of said second counter; and reading the output count of said third counter after said second counter goes beyond said predetermined output count, said third counter output count being representative of the duration of said selected pulse.
Claim 11
Dependent Claim
168 words
A circuit for measuring the duration of a selected pulse in a pulse train, said circuit comprising: a first counter for producing a pulse count enable logic signal pulse in response to a start pulse, said pulse count enable logic signal pulse having a duration at least as long as two sequences of pulses in an inverter drive logic signal; a second counter for counting transition points in said inverter drive logic signal, said second counter being activated by said pulse count enable logic signal pulse, and counting down from a predetermined initial count representative of a pulse in said inverter drive logic signal, the duration of which is to be measured; a third counter for counting clock pulses, said third counter being activated by a predetermined output count of said second counter; and means for reading the output count of said third counter after said second counter goes beyond said predetermined output count, said third counter output count being representative of the duration of said selected pulse.
Claim 12
Dependent Claim
168 words
A circuit for measuring the duration of a selected pulse in a pulse train, said circuit comprising: a first counter for producing a pulse count enable logic signal pulse in response to a start pulse, said pulse count enable logic signal pulse having a duration at least as long as two sequences of pulses in an inverter drive logic signal; a second counter for counting transition points in said inverter drive logic signal, said second counter being activated by said pulse count enable logic signal pulse, and counting down from a predetermined initial count representative of a pulse in said inverter drive logic signal, the duration of which is to be measured; a third counter for counting clock pulses, said third counter being activated by a predetermined output count of said second counter; and means for reading the output count of said third counter after said second counter goes beyond said predetermined output count, said third counter output count being representative of the duration of said selected pulse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-31 | 1994-07-02 | 1995-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-31 | 1998-07-02 | 1999-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-31 | 2002-07-02 | 2003-01-01 | $7700.00 | Window Closed / Lapsed |