US4982402A
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US
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Method and apparatus for detecting and correcting errors in a pipelined computer system
Assignee: Hewlett Packard Development Co LP
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Filing: 1989-02-03
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Granted: 1991-01-01
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Expires: 2009-02-03
Abstract
Abstract In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current instruction). Since synchronous errors prevent continued execution of the current instruction, it is preferable that the last stable state conditions of the faulting CPU be restored and the faulting instruction reexecuted. These stable state conditions advantageously occur between the execution of each instruction. However, in a pipelined computer system, it is difficult to identify the beginning and ending of a selected instruction since multiple instructions are in process at the same time. Accordingly, the execution unit is selected to be the point of synchronization between error handling and instruction execution. Once the error is indentified as asynchronous or synchronous and the execution unit allows the instruction to complete or rolls back the state conditions to their preinstruction values, error analyzing software examines the condition of the suspect data latches in the CPU. A serial diagnostic link stops the system clock of the CPU and serially loads the CPU data latches into the System Processor Unit for error determination. Thereafter, the CPU system clock is restarted and the CPU resumes execution.
Inventors
- 👤 Richard C. Beaven
- 👤 Michael B. Evans
- 👤 Tryggve Fossum
- 👤 Ricky C. Hetherington
- 👤 William R. Grundmann
- 👤 John E. Murray
- 👤 Ronald M. Salett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:57
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0724; G06F11/0766; G06F11/0772; G06F11/0781; G06F11/14; G06F11/1402; G06F11/1405; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
187 words
A method of handling errors in a pipelined central processing unit of a multiple central processing unit computer system, said central processing unit having an instruction unit for fetching and decoding instructions, an execution unit for executing instructions, and a system clock for clocking said instruction unit and said execution unit, said method comprising the steps of: detecting an error and delivering an error signal to the execution unit; determining if the detected error is synchronous and thereby prevents complete execution of an instruction currently being executed by the execution unit; restoring state conditions of said computer system to their status immediately prior to the beginning of the execution of the current instruction in response to the error being synchronous; allowing the execution of the current instruction to complete in response to the error being asynchronous and thereby having no effect on the complete execution of the instruction currently being executed by the execution unit; halting the system clock of the central processing unit; shifting the contents of selected central processor unit latches out of the central processing unit; and restarting the central processing unit system clock.
Claim 2
Independent Claim
187 words
A method of handling errors in a pipelined central processing unit of a multiple central processing unit computer system, said central processing unit having an instruction unit for fetching and decoding instructions, an execution unit for executing instructions, and a system clock for clocking said instruction unit and said execution unit, said method comprising the steps of: detecting an error and delivering an error signal to the execution unit; determining if the detected error is synchronous and thereby prevents complete execution of an instruction currently being executed by the execution unit; restoring state conditions of said computer system to their status immediately prior to the beginning of the execution of the current instruction in response to the error being synchronous; allowing the execution of the current instruction to complete in response to the error being asynchronous and thereby having no effect on the complete execution of the instruction currently being executed by the execution unit; halting the system clock of the central processing unit; shifting the contents of selected central processor unit latches out of the central processing unit; and restarting the central processing unit system clock.
Claim 3
Dependent Claim
36 words
A method, as set forth in claim 1, wherein said central processing unit has an instruction pipeline, and wherein said method further comprises the step of pipelining the error signal in parallel with the instruction pipeline.
Claim 4
Dependent Claim
35 words
A method, as set forth in claim 1, wherein said central processing unit has an instruction pipeline, and wherein the step of delivering an error signal to the execution unit includes bypassing the instruction pipeline.
Claim 5
Dependent Claim
52 words
A method, as set forth in claim 1, further comprising the step of supplying a memory clocking signal to memory to transfer memory data from said memory to said selected central processing unit latches so that said memory data is serially shifted from said latches and out of the central processing unit.
Claim 6
Dependent Claim
47 words
A method, as set forth in claim 1, wherein the step of shifting the contents of selected central processing unit latches includes shifting the data through a single master/slave latch pair in response to a single transition in each of a pair of non-overlapping scan clock signals.
Claim 7
Dependent Claim
100 words
A method, as set forth in claim 5, wherein the step or shifting data includes delivering a selected one of the non-overlapping scan clock signals to a clock input of the master latch, delivering the other non-overlapping scan clock signal to a clock input of the slave latch, delivering the contents of the master latch to the slave latch in response to the master latch receiving the selected one of the non-overlapping scan clock signals, and receiving the contents of the master latch into the slave latch in response to the slave latch receiving the other non-overlapping scan clock signal.
Claim 8
Independent Claim
240 words
An apparatus for handling errors in a pipelined central processing unit of a multiple central processing unit computer system, the central processing unit having an instruction pipeline adapted for processing an instruction in a series of discrete steps wherein each discrete processing step is performed simultaneous with discrete processing steps of other instructions, whereby multiple instructions are concurrently processed, one of the discrete processing steps being execution of the instruction by an execution unit having a system clock for clocking said processing unit having a system clock for clocking said instruction pipeline, said apparatus comprising: means for detecting an error and delivering an error signal to the execution unit; means for determining if the detected error is synchronous and thereby prevents complete execution of the instruction currently being executed by the execution unit; means for restoring state conditions of the computer system to their status immediately prior to the beginning of the execution of the current instruction in response to the error being synchronous; means for allowing the execution of the current instruction to complete in response to the error being asynchronous and thereby having no effect on the complete execution of the instruction currently being executed by the execution unit; means for halting the system clock of the central processing unit; means for serially shifting the contents of selected central processing unit latches out of the central processing unit; and means for restarting the central processing unit system clock.
Claim 9
Independent Claim
240 words
An apparatus for handling errors in a pipelined central processing unit of a multiple central processing unit computer system, the central processing unit having an instruction pipeline adapted for processing an instruction in a series of discrete steps wherein each discrete processing step is performed simultaneous with discrete processing steps of other instructions, whereby multiple instructions are concurrently processed, one of the discrete processing steps being execution of the instruction by an execution unit having a system clock for clocking said processing unit having a system clock for clocking said instruction pipeline, said apparatus comprising: means for detecting an error and delivering an error signal to the execution unit; means for determining if the detected error is synchronous and thereby prevents complete execution of the instruction currently being executed by the execution unit; means for restoring state conditions of the computer system to their status immediately prior to the beginning of the execution of the current instruction in response to the error being synchronous; means for allowing the execution of the current instruction to complete in response to the error being asynchronous and thereby having no effect on the complete execution of the instruction currently being executed by the execution unit; means for halting the system clock of the central processing unit; means for serially shifting the contents of selected central processing unit latches out of the central processing unit; and means for restarting the central processing unit system clock.
Claim 10
Dependent Claim
26 words
An apparatus, as set forth in claim 7, wherein the error detecting means includes means for pipelining the error signal in parallel with the instruction pipeline.
Claim 11
Dependent Claim
24 words
An apparatus, as set forth in claim 7, wherein the error detecting means includes means for the error signal to bypass the instruction pipeline.
Claim 12
Dependent Claim
68 words
An apparatus, as set forth in claim 7, wherein the means for serially shifting includes a plurality of master and slave latching means being serially connected together for shifting data from each pair of the master and slave latching means into a subsequent pair of the master and slave latching means in response to receiving a single pulse in each of a pair of non-overlapping scan clock signals.
Claim 13
Dependent Claim
98 words
An apparatus, as set forth in claim 10, wherein the means for serially shifting includes means for delivering a selected one of the non-overlapping scan clock signals to the master latching means, delivering the other non-overlapping scan clock signal to the slave latching means, delivering the contents of the master latching means to the slave latching means in response to the master latch receiving the selected one of the non-overlapping scan clock signals, and receiving the contents of the master latch into the slave latch in response to the slave latch receiving the other non-overlapping scan clock signal.
Claim 14
Dependent Claim
100 words
An apparatus, as set forth in claim 11, wherein the master latching means includes a master latch having a first data input connected to an input from a logic circuit associated with normal operation of the central processing unit and a second data input connected to the output of a serially prior slave latching means, said master latch being adapted to store the first data input therein in response to a transition in the system clock signal and to store the second data input therein in response to a transition in the selected one of the non-overlapping scan clock signals.
Claim 15
Dependent Claim
50 words
An apparatus, as set forth in claim 12, wherein the slave latching means includes a slave latch having a data input connected to the output of the master latch and being adapted for storing the data input therein in response to a transition in the other non-overlapping scan clock signal.
Claim 16
Dependent Claim
288 words
In a multi-processor computer system having at least one pipelined central processor unit and a service processor, an apparatus for handling errors in said pipelined central processing unit, said central processing unit having an instruction pipeline adapted for processing an instruction in a series of discrete steps wherein each discrete processing step is performed simultaneous with discrete processing steps of other instructions, whereby multiple instructions are concurrently processed, one of the discrete processing steps being execution of the instruction by an execution unit of the central processing unit, said central processing unit having a system clock for clocking said instruction pipeline, said apparatus comprising: means for detecting an error and delivering an error signal to the execution unit, said means for detecting an error including means for pipelining the error signal in parallel with the instruction pipeline; means for determining if the detected error is synchronous and thereby prevents complete execution of the instruction currently being executed by the execution unit; means for restoring state conditions of said central processing unit to their status immediately prior to the beginning of the execution of the current instruction in response to the error being synchronous; means for allowing the execution of the current instruction to complete in response to the error being asynchronous and thereby having no effect on the complete execution of the instruction currently being executed by the execution unit; means for halting the system clock of the central processing unit; means for serially shifting the contents of selected central processing unit latches out of the central processing unit and into said service processor for error determination; means for resetting the central processing unit to an appropriate state; and means for restarting the central processing unit system clock.
Claim 17
Dependent Claim
288 words
In a multi-processor computer system having at least one pipelined central processor unit and a service processor, an apparatus for handling errors in said pipelined central processing unit, said central processing unit having an instruction pipeline adapted for processing an instruction in a series of discrete steps wherein each discrete processing step is performed simultaneous with discrete processing steps of other instructions, whereby multiple instructions are concurrently processed, one of the discrete processing steps being execution of the instruction by an execution unit of the central processing unit, said central processing unit having a system clock for clocking said instruction pipeline, said apparatus comprising: means for detecting an error and delivering an error signal to the execution unit, said means for detecting an error including means for pipelining the error signal in parallel with the instruction pipeline; means for determining if the detected error is synchronous and thereby prevents complete execution of the instruction currently being executed by the execution unit; means for restoring state conditions of said central processing unit to their status immediately prior to the beginning of the execution of the current instruction in response to the error being synchronous; means for allowing the execution of the current instruction to complete in response to the error being asynchronous and thereby having no effect on the complete execution of the instruction currently being executed by the execution unit; means for halting the system clock of the central processing unit; means for serially shifting the contents of selected central processing unit latches out of the central processing unit and into said service processor for error determination; means for resetting the central processing unit to an appropriate state; and means for restarting the central processing unit system clock.
Claim 18
Dependent Claim
68 words
An apparatus, as set forth in claim 14, wherein said means for serially shifting includes a plurality of master and slave latching means being serially connected together for shifting data from each pair of the master and slave latching means into a subsequent pair of the master and slave latching means in response to receiving a single pulse in each of a pair of non-overlapping scan clock signals.
Claim 19
Dependent Claim
101 words
An apparatus, as set forth in claim 15, wherein the means for serially shifting includes means for delivering ga selected one of the non-overlapping scan clock signals to the master latching means, delivering the other non-overlapping scan clock signal to the slave latching means, delivering the contents of the master latching means to the slave latching means in response to the master latching means receiving the selected one of the non-overlapping scan clock signals, and receiving the contents of the master latch into the slave latching means in response to the salve latching means receiving the other non-overlapping scan clock signal.
Claim 20
Dependent Claim
100 words
An apparatus, as set forth in claim 16, wherein the master latching means includes a master latch having a first data input connected to an input from a logic circuit associated with normal operation of the central processing unit and a second data input connected to the output of a serially prior slave latching means, said mater latch being adapted to store the first data input therein in response to a transition in the system clock signal and to store the second data input therein in response to a transition in the selected one of the non-overlapping scan clock signals.
Claim 21
Dependent Claim
50 words
An apparatus, as set forth in claim 17, wherein the slave latching means includes a slave latch having a data input connected to the output of the master latch and being adapted for storing the data input therein in response to a transition in the other non-overlapping scan clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-31 | 1994-07-02 | 1995-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-31 | 1998-07-02 | 1999-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-31 | 2002-07-02 | 2003-01-01 | $7700.00 | Window Closed / Lapsed |