Computer for synchronized read and write of vector data

Claim 2

A computer comprising: (a) a main storage; (b) a writing means responsive to at least one first program instruction for writing a group of ordered data elements designated by the first program instruction into arbitrary locations within said main storage; (c) a reading means responsive to at least one second program instruction for reading said group of data elements from said main storage; and, (d) an access controlling means connected to said writing means and said reading means and responsive to the at least one first instruction and the at least one second instruction for controlling access by said reading means to inhibit said reading means from trying to read each data element among said group of data elements before the each data element has been written by said writing means, said controlling means including: a register for holding status signals each of which indicates whether a corresponding one of said group of data elements has been written into said main storage, irrespective of the locations within said main memory in which the group of data elements are written; a first means connected to said register and responsive to the at least one register and responsive to the at least one first instruction for writing status signals that respectively represent completion of writing each corresponding data element of the group of data elements into a corresponding position of said register, in synchronism with completion of writing of the corresponding data element onto said main storage by said writing means and irrespective of location within said main memory in which the group of data elements is written; and a second means connected to said register and to said reading means and responsive to the at least one second instruction for inhibiting the reading means for reading each element of the group of data elements until the status signal is stored in said register for the corresponding data element.

Claim 3

A computer according to claim 1, wherein said first means has means for writing the status signal that indicates the completion of writing for each of the data elements onto said register, in response to each of the write finish signals which is supplied from said main storage when the data element has been written onto said main storage.

Claim 4

A computer according to claim 1, wherein said first means has means for generating an element number of a data element written by said writing means, in synchronism with writing thereof by said writing means, and for sending to said register said element number to indicate a position in said register in which the status signal that indicates completion of writing is to be written.

Claim 5

A computer according to claim 1, wherein said computer has first and second processors connected to said main storage, and said writing means and said reading means are contained in said first and second processors, respectively.

Claim 6

A computer according to claim 1, wherein said computer has at least one processor connected to said main storage, and said writing means and said reading means are contained in said processor.

Claim 7

A computer comprising: (a) a main storage; (b) a vector processor connected to said main storage, the vector processor including: a writing means responsive to a vector store instruction executed by the vector processor for sequentially writing vector elements of first vector data into locations within said main storage designated by the vector store instruction, and a reading means responsive to a vector load instruction for reading vector elements of second vector data from locations within said main storage designated by the vector load instruction; (c) a plurality of element processors connected to said main storage, each element processor including: access means responsive to a data load instruction executed by the element processor for reading a corresponding vector element of said first vector data from a location within said main storage designated by the data load instruction and responsive to a data store instruction executed by the element processor for writing a corresponding vector element of said second vector data onto a location within said main storage designated by the data store instruction; and (d) a controlling means connected to said vector processor and to said plurality of element processors for controlling transfer of the first and second vector data via said main storage between said vector processor and said plurality of element processors such that the element processors are inhibited from reading respective vector elements of said first vector data from said main storage before said vector processor writes the vector elements into said main storage, and such that the vector processor is inhibited from reading respective vector elements of said second vector elements from said main storage before said plurality of element processors write the vector element into said main storage, said controlling means including: a register for holding status signals each of which indicates whether a corresponding vector element of vector data to be transferred via said main storage between said vector processor and said plurality of element processors has been written into said main storage, irrespective of locations within said main memory into which said vector data to be transferred is written; a first means connected to said register and responsive to the vector store instruction for writing status signals that respectively represent completion of writing corresponding vector elements of the first vector data into positions corresponding to the written vector elements within said register, in synchronism with the completion of writing of the corresponding vector elements into said main storage by said writing means and irrespective of locations within said main memory into which the vector elements of the first vector data are written and responsive to the data write instruction executed by one of the element processor writing a status signal indicative of completion of writing for a corresponding vector element of the second vector data into a position corresponding to the written vector element within said register and in synchronism with completion of writing of the vector element of the second vector data onto said main storage by said access means within said one element processor; and a second means connected to said register, said reading means of said vector processor and said access means of each element processor and responsive to said vector load instruction for inhibiting each of said vector elements of the second vector data from being read by said reading means of said vector processor until the status signal indicative of completion of writing for the vector element is stored in said register for the corresponding vector element and responsive to said data load instruction executed by one of said plurality of element processors for inhibiting a corresponding vector element designated by the vector store instruction of the first data from being read by said access means within the corresponding one of the element processors until the status signal indicative of completion of writing is stored in said register for the corresponding vector element.

Claim 8

A computer comprising: (a) a main storage; (b) a vector processor connected to said main storage, the vector processor including: a writing means responsive to a vector store instruction executed by the vector processor for sequentially writing vector elements of first vector data into locations within said main storage designated by the vector store instruction, and a reading means responsive to a vector load instruction for reading vector elements of second vector data from locations within said main storage designated by the vector load instruction; (c) a plurality of element processors connected to said main storage, each element processor including: access means responsive to a data load instruction executed by the element processor for reading a corresponding vector element of said first vector data from a location within said main storage designated by the data load instruction and responsive to a data store instruction executed by the element processor for writing a corresponding vector element of said second vector data onto a location within said main storage designated by the data store instruction; and (d) a controlling means connected to said vector processor and to said plurality of element processors for controlling transfer of the first and second vector data via said main storage between said vector processor and said plurality of element processors such that the element processors are inhibited from reading respective vector elements of said first vector data from said main storage before said vector processor writes the vector elements into said main storage, and such that the vector processor is inhibited from reading respective vector elements of said second vector elements from said main storage before said plurality of element processors write the vector element into said main storage, said controlling means including: a register for holding status signals each of which indicates whether a corresponding vector element of vector data to be transferred via said main storage between said vector processor and said plurality of element processors has been written into said main storage, irrespective of locations within said main memory into which said vector data to be transferred is written; a first means connected to said register and responsive to the vector store instruction for writing status signals that respectively represent completion of writing corresponding vector elements of the first vector data into positions corresponding to the written vector elements within said register, in synchronism with the completion of writing of the corresponding vector elements into said main storage by said writing means and irrespective of locations within said main memory into which the vector elements of the first vector data are written and responsive to the data write instruction executed by one of the element processor writing a status signal indicative of completion of writing for a corresponding vector element of the second vector data into a position corresponding to the written vector element within said register and in synchronism with completion of writing of the vector element of the second vector data onto said main storage by said access means within said one element processor; and a second means connected to said register, said reading means of said vector processor and said access means of each element processor and responsive to said vector load instruction for inhibiting each of said vector elements of the second vector data from being read by said reading means of said vector processor until the status signal indicative of completion of writing for the vector element is stored in said register for the corresponding vector element and responsive to said data load instruction executed by one of said plurality of element processors for inhibiting a corresponding vector element designated by the vector store instruction of the first data from being read by said access means within the corresponding one of the element processors until the status signal indicative of completion of writing is stored in said register for the corresponding vector element.

Claim 9

A computer according to claim 6, wherein said first means has means for writing the status signal that indicates completion of writing each of the vector elements onto said register, in response to write finish signals which are supplied from said main storage when the vector elements have been written into said main storage.

Claim 10

A computer according to claim 6, wherein said first means has means for generating an element number of a vector element written by said writing means, in synchronism with writing thereof by said writing means, and for sending to said register said element number to indicate a position in said register in which the status signal that indicates completion of writing is to be written.

Claim 11

A computer comprising: (a) a main storage; (b) at least one vector processor connected to said main storage, each vector processor including: at least one writing means responsive to vector store instruction executed by the vector processor for sequentially writing a group of vector elements into said main storage, and at least one reading means responsive to a vector load instruction for sequentially reading the group of vector elements from said main storage; and (c) a controlling means connected to said writing means and said reading means for controlling transfer of the vector data via said main storage between said writing means and said reading means such that said reading means in inhibited from reading vector elements that have not yet been written by said writing means, said controlling means including: a register for holding status signals each of which indicates whether a corresponding vector element has been written into said main storage, irrespective of locations within said main storage where the vector elements are written; first means connected to said register and responsive to the vector store instruction for writing status signals that respectively represent completion of writing onto positions in said register corresponding to the respective vector elements, each in synchronism with completion of writing of each of the vector elements onto said main storage by said writing means and irrespective of locations within said main storage where the vector elements are written; and second means connected to said register, and to said reading means and responsive to the vector load instruction for inhibiting each of said vector elements from being read by said reading means until the status signal that represents completion of writing for the corresponding vector element is stored in said register.

Claim 12

A computer comprising: (a) a main storage; (b) at least one vector processor connected to said main storage, each vector processor including: at least one writing means responsive to vector store instruction executed by the vector processor for sequentially writing a group of vector elements into said main storage, and at least one reading means responsive to a vector load instruction for sequentially reading the group of vector elements from said main storage; and (c) a controlling means connected to said writing means and said reading means for controlling transfer of the vector data via said main storage between said writing means and said reading means such that said reading means in inhibited from reading vector elements that have not yet been written by said writing means, said controlling means including: a register for holding status signals each of which indicates whether a corresponding vector element has been written into said main storage, irrespective of locations within said main storage where the vector elements are written; first means connected to said register and responsive to the vector store instruction for writing status signals that respectively represent completion of writing onto positions in said register corresponding to the respective vector elements, each in synchronism with completion of writing of each of the vector elements onto said main storage by said writing means and irrespective of locations within said main storage where the vector elements are written; and second means connected to said register, and to said reading means and responsive to the vector load instruction for inhibiting each of said vector elements from being read by said reading means until the status signal that represents completion of writing for the corresponding vector element is stored in said register.

Claim 13

A computer according to claim 9, wherein said first means has means for writing the status signal that indicates completion of writing for each of the vector elements onto said register, in response to each of a plurality of write finish signals which are supplied from said main storage when each vector element has been written into said main storage.

Claim 14

A computer according to claim 9, wherein said first means has means for generating an element number of a vector element written by said writing means, in synchronism with writing thereof by said writing means, and for sending to said register said element number to indicate a position in said register of the status signal that indicates completion of writing is to be written.

Claim 15

A computer comprising: (a) a main storage; (b) first and second vector processors connected to said main storage, each vector processor having: a writing means responsive to a vector store instruction executed by one of said first and second vector processors for sequentially writing a group of vector data elements onto said main storage, and a reading means responsive to a vector load instruction executed by another of said first and second vector processors for sequentially reading the group of vector data elements from said main storage; and (c) a controlling means connected to said writing means and said reading means provided in each of said first and second vector processors for controlling transfer of the vector data elements via said main memory between said first and second vector processors such that each vector processor is inhibited from reading vector data elements before each is written by the other vector processor, said controlling means including: a register for holding status signals each of which indicates whether a corresponding one of said group of vector elements have been written into said main storage, irrespective of locations within said main storage where the group of vector data elements are written; first means connected to said register and responsive to the vector store instruction for writing status signals that respectively represent completion of writing of a corresponding one of the group of vector elements onto corresponding positions of said register, in synchronism with completion of writing of the corresponding vector elements onto said main storage by said writing means and irrespective of locations within said main storage where the group of vector elements are written; and second means connected to said register and to said reading means and responsive to the vector load instruction for inhibiting each of said vector elements from being read by said reading means until the corresponding status signal is stored in said register for the vector element.

Claim 16

A computer comprising: (a) a main storage; (b) first and second vector processors connected to said main storage, each vector processor having: a writing means responsive to a vector store instruction executed by one of said first and second vector processors for sequentially writing a group of vector data elements onto said main storage, and a reading means responsive to a vector load instruction executed by another of said first and second vector processors for sequentially reading the group of vector data elements from said main storage; and (c) a controlling means connected to said writing means and said reading means provided in each of said first and second vector processors for controlling transfer of the vector data elements via said main memory between said first and second vector processors such that each vector processor is inhibited from reading vector data elements before each is written by the other vector processor, said controlling means including: a register for holding status signals each of which indicates whether a corresponding one of said group of vector elements have been written into said main storage, irrespective of locations within said main storage where the group of vector data elements are written; first means connected to said register and responsive to the vector store instruction for writing status signals that respectively represent completion of writing of a corresponding one of the group of vector elements onto corresponding positions of said register, in synchronism with completion of writing of the corresponding vector elements onto said main storage by said writing means and irrespective of locations within said main storage where the group of vector elements are written; and second means connected to said register and to said reading means and responsive to the vector load instruction for inhibiting each of said vector elements from being read by said reading means until the corresponding status signal is stored in said register for the vector element.

Claim 17

A computer according to claim 12, wherein said first means includes means for writing the status signal that indicates completion of writing for each of the vector elements onto said register, in response to write finish signals which are supplied from said main storage when the vector elements are respectively written into said main storage.

Claim 18

A computer according to claim 12, wherein said first means has means for generating an element number of a vector element written by said writing means, in synchronism with writing thereof by said writing means, and for sending to said register said element number to indicate a position in said register in which to write the status signal that indicates completion of writing.