Non-volatile memory cell

Claim 2

In a non-volatile memory cell array including a plurality of non-volatile memory cells which are formed at a surface of a semiconductor substrate and which each includes spaced source and drain zones formed in said surface, a trench provided in said surface adjacent the side of said drain zone facing away from the channel zone, a tunnel through dielectric layer disposed on said surface and covering at least the side walls of said trench, and a floating-gate electrode, as the memory electrode, disposed on said dielectric layer and extending into said trench; the improvement wherein: said drain zone of at lest two of said non-volatile memory cells are disposed adjacent a single said trench and said floating-gate electrodes of said at lest two memory cells extend into said signal trench so that tunnel current can flow horizontally to the semiconductor surface between a respective said drain zone and the associated one of said floating-gate-electrodes.

Claim 3

A non-volatile memory cell array according to claim 1, wherein said trench is rectangular and wherein a respective portion of a side wall of said single trench is covered by each of said floating-gate electrodes of said at least two memory cells.

Claim 4

A non-volatile memory cell array according to claim 2, wherein said trench has a depth of approximately 1.5 μm.

Claim 5

A non-volatile memory cell array according to claim 1, wherein said floating-gate electrodes of said at least two memory cells are arranged radially around said trench.

Claim 6

A non-volatile memory cell array according to claim 2, wherein the two said floating-gate electrodes cover portions of two opposite side walls of said rectangular trench.

Claim 7

An array according to claim 1, wherein said trench is deeper than said drain zones.

Claim 8

An array according to claim 1, wherein said trench is symmetrically disposed between two identical said drain zones.

Claim 9

An array according to claim 1, wherein said semiconductor substrate comprises silicon.

Claim 10

An array according to claim 1, wherein said gate electrodes comprise polysilicon.

Claim 11

In a non-volatile memory cell array including at least first and second non-volatile memory cells formed on a semiconductor substrate and each including a floating-gate field effect transistor having spaced source and drain zones formed in a surface of said semiconductor substrate and defining a channel zone therebetween, and a floating-gate electrode, which serves as the memory electrode, arranged on a tunnel-through dielectric layer disposed on said surface of said semiconductor substrate; the improvement wherein: a single trench is formed in said surface of said semiconductor element adjacent the side of the drain zone which faces away from the respective said channel zone of at least each of said first and second memory cells; said dielectric layer covers at least the side walls of said trench; and said floating gate electrode of each of said first and second memory cells extends along said dielectric layer into said trench and over respective portions of said side walls such that tunnel current can flow horizontally to the semiconductor surface between said drain zones and respectively associated said floating-gate electrodes.

Claim 12

In a non-volatile memory cell array including at least first and second non-volatile memory cells formed on a semiconductor substrate and each including a floating-gate field effect transistor having spaced source and drain zones formed in a surface of said semiconductor substrate and defining a channel zone therebetween, and a floating-gate electrode, which serves as the memory electrode, arranged on a tunnel-through dielectric layer disposed on said surface of said semiconductor substrate; the improvement wherein: a single trench is formed in said surface of said semiconductor element adjacent the side of the drain zone which faces away from the respective said channel zone of at least each of said first and second memory cells; said dielectric layer covers at least the side walls of said trench; and said floating gate electrode of each of said first and second memory cells extends along said dielectric layer into said trench and over respective portions of said side walls such that tunnel current can flow horizontally to the semiconductor surface between said drain zones and respectively associated said floating-gate electrodes.