US4991136A
Expired / Lapsed
US
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Semiconductor associative memory device with memory refresh during match and read operations
Assignee: Mitsubishi Electric Corp
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Filing: 1989-01-30
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Granted: 1991-02-05
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Expires: 2009-01-30
Abstract
Abstract A semiconductor associative memory device comprises a content addressable memory cell connected to a word line, a bit line, an inversion bit line and a match line. The memory cell comprises first and second n channel MOS transistors constituting a capacitance element. When the word line is activated, a value on the bit line is stored in the first n channel MOS transistor, and the value on the inversion bit line is stored in the second n channel MOS transistor. When the first n channel MOS transistor and the bit line are in the active state, or when the second n channel MOS transistor and the inversion bit line are in the active state, a control terminal is activated. N channel MOS transistors are connected between the control terminal and the first and second n channel MOS transistors, and the first and second n channel MOS transistors are refreshed during matching and reading by means of these transistors.
Inventors
- 👤 Masaaki Mihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:17
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G11C15/043
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
195 words
A semiconductor memory device having a content addressable memory cell connected to a word line, a bit line, an inversion bit line and a match line, wherein: said memory cell comprises: first control means, including first and second transistors and a control terminal, for applying a first predetermined potential to said control terminal when said first transistor is in an active state and said bit line is at a first level or when said second transistor is in an active state and said inversion bit line is at said first level; second control means for storing a level of said bit line on a gate capacitance of said first transistor and for storing a level of said inversion bit line on a gate capacitance of said second transistor when said word line is at an activation level; a first semiconductor element connected between said control terminal and a gate of said first transistor; a second semiconductor element connected between said control terminal and a gate of said second transistor; a third semiconductor element connected between said control terminal and said match line, which becomes conductive when said match line is at a second predetermined potential.
Claim 2
Dependent Claim
195 words
A semiconductor memory device having a content addressable memory cell connected to a word line, a bit line, an inversion bit line and a match line, wherein: said memory cell comprises: first control means, including first and second transistors and a control terminal, for applying a first predetermined potential to said control terminal when said first transistor is in an active state and said bit line is at a first level or when said second transistor is in an active state and said inversion bit line is at said first level; second control means for storing a level of said bit line on a gate capacitance of said first transistor and for storing a level of said inversion bit line on a gate capacitance of said second transistor when said word line is at an activation level; a first semiconductor element connected between said control terminal and a gate of said first transistor; a second semiconductor element connected between said control terminal and a gate of said second transistor; a third semiconductor element connected between said control terminal and said match line, which becomes conductive when said match line is at a second predetermined potential.
Claim 3
Dependent Claim
114 words
A semiconductor associative memory device according to claim 1, wherein said second control means comprises: a fourth semiconductor element including a gate electrode and first and second conductive terminals, said gate electrode connected to said word line, said first conductive terminal connected to said bit line and said second conductive terminal connected to said first transistor; and a fifth semiconductor element including a gate electrode and first and second conductive terminals, said gate electrode of said fifth semiconductor element connected to said word line, said first conductive terminal of said fifth semiconductor element connected to said inversion bit line and said second conductive terminal of said fifth semiconductor element connected to said second transistor.
Claim 4
Dependent Claim
69 words
A semiconductor associative memory device according to claim 1 wherein said first transistor comprises: a gate electrode and first and second conductive terminals, said gate electrode of said first transistor connected to the second conductive terminal of said fourth semiconductor element; and a gate electrode and first and second conductive terminals, said gate electrode of said second transistor connected to the second conductive terminal of said fifth semiconductor element.
Claim 5
Dependent Claim
358 words
A semiconductor associative memory device having a content addressable memory cell connected to a word line, a bit line, an inversion bit line and a match line, wherein said memory cell comprises: a first semiconductor element including a gate electrode and first and second conductive terminals, said gate electrode connected to said word line, and said first conductive terminal connected to said bit line; a second semiconductor element having a gate electrode and first and second conductive terminals, said gate electrode of said second semiconductor element connected to said word line and said first conductive terminal of said second semiconductor element connected to said inversion bit line; a third semiconductor element having a gate electrode and first and second conductive terminals, said gate electrode of said third semiconductor element connected to the second conductive terminal of said first semiconductor element and said first conductive terminal of said third semiconductor element connected to said bit line; a fourth semiconductor element having a gate electrode and first and second conductive terminals, said gate electrode of said fourth semiconductor element connected to the second conductive terminal of said second semiconductor element and said first conductive terminal of said fourth semiconductor element connected to said inversion bit line; a fifth semiconductor element having a gate electrode and first and second conductive terminals, said gate electrode of said fifth semiconductor element connected to said bit line and said first conductive terminal of said fifth semiconductor element connected to the gate electrode of said third semiconductor element; a sixth semiconductor element having a gate electrode and first and second conductive terminals, said gate electrode of said sixth semiconductor element connected to said inversion bit line and said first conductive terminal of said sixth semiconductor element connected to the gate electrode of said fourth semiconductor element; and a seventh semiconductor element having a gate electrode and first and second conductive terminals, said gate electrode and said second conductive terminal of said seventh semiconductor element connected to said match line and said first conductive terminal of said seventh semiconductor element connected to the respective second conductive terminals of said third, fourth, fifth and sixth semiconductor elements.
Claim 6
Dependent Claim
358 words
A semiconductor associative memory device having a content addressable memory cell connected to a word line, a bit line, an inversion bit line and a match line, wherein said memory cell comprises: a first semiconductor element including a gate electrode and first and second conductive terminals, said gate electrode connected to said word line, and said first conductive terminal connected to said bit line; a second semiconductor element having a gate electrode and first and second conductive terminals, said gate electrode of said second semiconductor element connected to said word line and said first conductive terminal of said second semiconductor element connected to said inversion bit line; a third semiconductor element having a gate electrode and first and second conductive terminals, said gate electrode of said third semiconductor element connected to the second conductive terminal of said first semiconductor element and said first conductive terminal of said third semiconductor element connected to said bit line; a fourth semiconductor element having a gate electrode and first and second conductive terminals, said gate electrode of said fourth semiconductor element connected to the second conductive terminal of said second semiconductor element and said first conductive terminal of said fourth semiconductor element connected to said inversion bit line; a fifth semiconductor element having a gate electrode and first and second conductive terminals, said gate electrode of said fifth semiconductor element connected to said bit line and said first conductive terminal of said fifth semiconductor element connected to the gate electrode of said third semiconductor element; a sixth semiconductor element having a gate electrode and first and second conductive terminals, said gate electrode of said sixth semiconductor element connected to said inversion bit line and said first conductive terminal of said sixth semiconductor element connected to the gate electrode of said fourth semiconductor element; and a seventh semiconductor element having a gate electrode and first and second conductive terminals, said gate electrode and said second conductive terminal of said seventh semiconductor element connected to said match line and said first conductive terminal of said seventh semiconductor element connected to the respective second conductive terminals of said third, fourth, fifth and sixth semiconductor elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-04 | 1994-08-06 | 1995-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-04 | 1998-08-06 | 1999-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-04 | 2002-08-06 | 2003-02-05 | $7700.00 | Window Closed / Lapsed |