US4997785A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Shared gate CMOS transistor
Assignee: Motorola Solutions Inc
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Filing: 1989-09-05
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Granted: 1991-03-05
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Expires: 2009-09-05
Abstract
Abstract A stacked shared-gate CMOS transistor and method of fabrication are disclosed. An improved CMOS transistor is fabricated by the formation of a bulk transistor and an overlying isolated (SOI) transistor wherein each transistor is adjoined to a portion of a shared gate having the same conductivity type as the related transistor. The differential conductivity of the shared gate is obtained by the fabrication of a conductive diffusion-barrier layer intermediate to conductive layers. Improved switching performance is obtained as a result of higher current levels produced by the isolated transistor.
Inventors
- 👤 James R. Pfiester
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:13
CPC Classifications
H; H10; H10D; H10D88/00; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/01
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
210 words
A process for fabricating a shared-gate stacked, CMOS transistor structure comprising the steps of: providing a silicon substrate having an active region; forming a dielectric layer to overlie said active region; forming a first conductive layer of a first conductivity type to overlie said dielectric layer; forming a barrier layer to overlie said first conductive layer; forming a second conductive layer of a second conductivity type to overlie said barrier layer; forming an etch mask to overlie said second conductive layer; anisotropically etching said second conductive layer, said barrier layer, and said first conductive layer to form a self-aligned shared gate, said gate being located in said active region; forming an impurity region of a first conductivity type in said active region of said substrate using said etch mask as a dopant mask; removing said etch mask; forming an insulation layer to overlie said shared gate and said active region; forming a third conductive layer of a second conductivity type to overlie said insulation layer; forming a mask to overlie said third conductive layer said mask being located over a central portion of said shared gate; doping said third conductive layer with a dopant of a second conductivity type using said mask as a dopant mask; and removing said mask.
Claim 2
Dependent Claim
210 words
A process for fabricating a shared-gate stacked, CMOS transistor structure comprising the steps of: providing a silicon substrate having an active region; forming a dielectric layer to overlie said active region; forming a first conductive layer of a first conductivity type to overlie said dielectric layer; forming a barrier layer to overlie said first conductive layer; forming a second conductive layer of a second conductivity type to overlie said barrier layer; forming an etch mask to overlie said second conductive layer; anisotropically etching said second conductive layer, said barrier layer, and said first conductive layer to form a self-aligned shared gate, said gate being located in said active region; forming an impurity region of a first conductivity type in said active region of said substrate using said etch mask as a dopant mask; removing said etch mask; forming an insulation layer to overlie said shared gate and said active region; forming a third conductive layer of a second conductivity type to overlie said insulation layer; forming a mask to overlie said third conductive layer said mask being located over a central portion of said shared gate; doping said third conductive layer with a dopant of a second conductivity type using said mask as a dopant mask; and removing said mask.
Claim 3
Dependent Claim
19 words
The process of claim 1 wherein said first conductivity type is N-type and said second conductivity type is P-type.
Claim 4
Dependent Claim
19 words
The process of claim 1 wherein said first conductivity type is P-type and said second conductivity type is N-type.
Claim 5
Dependent Claim
40 words
The process of claim 2 wherein said step of forming a first conductive layer comprises forming a refractory metal silicide, said silicide is selected from the group consisting of titanium silicide, tungsten silicide, molybdenum silicide, tantalum silicide, and cobalt silicide.
Claim 6
Dependent Claim
33 words
The process of claim 4 wherein said step of forming a second conductive layer comprises the steps of: depositing a layer of polysilicon; and doping said layer of polysilicon with an acceptor atom.
Claim 7
Dependent Claim
40 words
The process of claim 3 wherein said step of forming a second conductive layer comprises forming a refractory metal silicide, said silicide is selected from the group consisting of titanium silicide, tungsten silicide, molybdenum silicide, tantalum silicide, and cobalt silicide.
Claim 8
Dependent Claim
33 words
The process of claim 6 wherein said step of forming a first conductive layer comprises the steps of: depositing a layer of polysilicon; and doping said layer of polysilicon with an acceptor atom.
Claim 9
Dependent Claim
85 words
The process of claim 2 wherein said step of forming a first conductive layer and said step of forming a barrier layer comprise the steps of: depositing a layer of polysilicon to overlie said dielectric layer; depositing a layer of titanium to overlie said polysilicon layer; and annealing said polysilicon layer and said titanium layer in a nitrogen atmosphere at about 650 to 700 degrees centigrade to form a layer of titanium silicide and a layer of titanium nitride overlying said layer of titanium silicide.
Claim 10
Dependent Claim
33 words
The process of claim 8 wherein said step of forming a second conductive layer comprises the steps of: depositing a layer of polysilicon; and doping said layer of polysilicon with an acceptor atom.
Claim 11
Independent Claim
209 words
A method for fabricating a semiconductor device comprising the steps of: forming a dielectric layer to overlie a surface of a P-type silicon substrate; depositing a first polysilicon layer to overlie said dielectric layer and doping said polysilicon layer with phosphorus; depositing a barrier layer by chemical vapor deposition to overlie said first polysilicon layer; depositing a second polysilicon layer to overlie said barrier layer; doping said second polysilicon layer with boron; forming photoresist mask to overlie said second polysilicon layer; anisotropically etching said second polysilicon layer, said barrier layer, and said first polysilicon layer to form a self-aligned shared gate; removing said photoresist mask; forming an N-type impurity region in said active region of said substrate by ion implantation using said shared gate as an ion implant mask; thermally oxidizing said substrate to form a layer of silicon dioxide overlying said shared gate and said surface of said substrate; depositing a third polysilicon layer to overlie said insulation layer; doping said third polysilicon layer with boron; forming a photoresist mask to overlie said third polysilicon layer, said mask being located over a central portion of said shared gate; ion implanting said third polysilicon layer with boron using said photoresist mask as a dopant mask; and removing said mask.
Claim 12
Independent Claim
209 words
A method for fabricating a semiconductor device comprising the steps of: forming a dielectric layer to overlie a surface of a P-type silicon substrate; depositing a first polysilicon layer to overlie said dielectric layer and doping said polysilicon layer with phosphorus; depositing a barrier layer by chemical vapor deposition to overlie said first polysilicon layer; depositing a second polysilicon layer to overlie said barrier layer; doping said second polysilicon layer with boron; forming photoresist mask to overlie said second polysilicon layer; anisotropically etching said second polysilicon layer, said barrier layer, and said first polysilicon layer to form a self-aligned shared gate; removing said photoresist mask; forming an N-type impurity region in said active region of said substrate by ion implantation using said shared gate as an ion implant mask; thermally oxidizing said substrate to form a layer of silicon dioxide overlying said shared gate and said surface of said substrate; depositing a third polysilicon layer to overlie said insulation layer; doping said third polysilicon layer with boron; forming a photoresist mask to overlie said third polysilicon layer, said mask being located over a central portion of said shared gate; ion implanting said third polysilicon layer with boron using said photoresist mask as a dopant mask; and removing said mask.
Claim 13
Dependent Claim
32 words
The method of claim 10 wherein said barrier layer comprises the chemical vapor deposition of a refractory metal nitride selected from the group consisting of titanium nitride, tantalum nitride, and chromium nitride.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-04 | 1994-09-03 | 1995-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-04 | 1998-09-03 | 1999-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-04 | 2002-09-03 | 2003-03-05 | $7700.00 | Window Closed / Lapsed |