Trench DRAM cell with dynamic gain

Claim 1

A semiconductor dynamic random access (DRAM) cell, comprising: a layered semiconductor formed on a substrate having a number of layers, the layered semiconductor having a trench formed therein, with sidewalls of the trench cut through the layers and with a bottom of the trench in the substrate; a dielectric formed along the sidewalls and bottom in said trench; a storage node material contacting the dielectric within the trench, the storage node material together with the dielectric and the substrate defining a storage capacitor; a vertical gain transistor including source and drain regions formed adjacent said trench, said storage node being a gate electrode and said dielectric defining a gate insulator of said vertical gain transistor; a terminal for connecting a voltage supply to the substrate and the drain region of said vertical gain transistor; the source region of said vertical gain transistor defining a portion of a bit line for providing a path for an output signal during read operations of said DRAM cell; a vertical pass transistor including source and drain regions formed adjacent said trench, said vertical pass transistor having a channel connected between said bit line and said storage node for providing charge to said DRAM cell during write operations thereof; and a gate electrode of the vertical pass transistor for connecting with a word line operative to control said vertical pass transistor during write operations and to control said vertical gain transistor during read operations.