Binary magnitude comparator with asynchronous compare operation and method therefor

Claim 2

A binary magnitude comparator cell for performing a comparison of a data output signal to a predetermined logic state in response to an enable input signal, comprising: data storage means, for providing the data output signal in response to a logic state of a data input signal during a predetermined time period; enable carry means coupled to the data storage means, for receiving the enable input signal, the data output signal, and a feedback signal, said enable input signal enabling a binary magnitude comparison, and for providing an enable carry signal, said enable carry signal provided in response to predetermined logic values of the enable input signal, the data output signal, and the feedback signal; and output drive means coupled to the data storage means, for receiving the data output signal and the enable input signal, and for comparing the data output signal with the predetermined logic state to provide a compare output signal in response to both the data output signal and a predetermined logic value of the enable input signal.

Claim 3

The binary magnitude comparator cell of claim 1, wherein the enable carry means provides said enable carry signal at a first logic state if the enable input signal and either the data output signal or the feedback signal are at the first logic state, and wherein the output drive means provides said compare output signal at a second logic state if the enable input signal and the data output signal are at the first logic state, or at a high impedance state otherwise.

Claim 4

The binary magnitude comparator cell of claim 2, wherein said enable carry means comprises: OR gate means, for receiving the data output signal and the feedback signal, and for providing an intermediate output signal having a logic state equal to the logical OR of the data output signal and the feedback signal; and AND gate means, coupled to the OR gate means, for receiving the enable input signal and the intermediate output signal of said OR gate, and for providing the carry output signal having a logic state equal to the logical AND of the enable input signal and the intermediate signal.

Claim 5

The binary magnitude comparator cell of claim 2, wherein said output drive means comprises: a first transistor, having a first current electrode for providing the compare output signal, a control electrode coupled to the enable input signal, and a second current electrode; and a second transistor, having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the data output signal, and a second current electrode coupled to a negative power supply voltage terminal.

Claim 6

A binary magnitude comparator, for receiving a plurality of select signals, and for providing a plurality of first output signals and a plurality of second output signals, comprising a plurality of columns, including a most significant column and a least significant column, each of said plurality of columns having an interconnect line and receiving a plurality of enable input signals, and providing one of said plurality of first output signals, and providing a plurality of enable carry signals, each column comprising: a sense amplifier coupled to the interconnect line, for comparing a voltage on the interconnect line with a first predetermined logic state, and providing said one of the plurality of first output signals in response thereto; and a plurality of binary magnitude comparator cells, each of said plurality of binary magnitude comparator cells receiving one of said plurality of enable input signals, and providing one of said plurality of enable carry signals, and providing a voltage on said interconnect line in response to said one of said plurality of enable input signals and to a comparison of a logic state of a memory bit associated therewith and a second predetermined logic state; wherein for all columns except the least significant column, the plurality of enable carry signals of a column provides the plurality of enable input signals of a next most significant column, wherein said plurality of select signals provides the plurality of enable input signals for the most significant column, and wherein the enable carry signals of the least significant column form the plurality of second output signals.

Claim 7

A binary magnitude comparator, for receiving a plurality of select signals, and for providing a plurality of first output signals and a plurality of second output signals, comprising a plurality of columns, including a most significant column and a least significant column, each of said plurality of columns having an interconnect line and receiving a plurality of enable input signals, and providing one of said plurality of first output signals, and providing a plurality of enable carry signals, each column comprising: a sense amplifier coupled to the interconnect line, for comparing a voltage on the interconnect line with a first predetermined logic state, and providing said one of the plurality of first output signals in response thereto; and a plurality of binary magnitude comparator cells, each of said plurality of binary magnitude comparator cells receiving one of said plurality of enable input signals, and providing one of said plurality of enable carry signals, and providing a voltage on said interconnect line in response to said one of said plurality of enable input signals and to a comparison of a logic state of a memory bit associated therewith and a second predetermined logic state; wherein for all columns except the least significant column, the plurality of enable carry signals of a column provides the plurality of enable input signals of a next most significant column, wherein said plurality of select signals provides the plurality of enable input signals for the most significant column, and wherein the enable carry signals of the least significant column form the plurality of second output signals.

Claim 8

A binary magnitude comparator having a plurality of rows and a plurality of columns, including a most significant column and a least significant column, comprising: a plurality of rows and columns of comparator cells, each of said plurality of comparator cells storing a data bit and comparing the stored data bit with a predetermined logic state to provide a first output signal, said data bit being in either a first logic state or a second logic state, and the first output signal being in the first logic state when an enable input signal coupled thereto is in the second logic state, and providing the first output signal in a high impedance state otherwise, and for providing an enable carry bit in the second logic state if either said stored data bit or a feedback signal are in the second logic state, and the enable input signal is in the second logic state, and otherwise providing the enable carry bit in the first logic state; and sense amplifier means, coupled to the plurality of comparator cells, for receiving the first output signal from each of said plurality of comparator cells, for providing a second output signal, a bit of said second output signal associated with each of said plurality of columns, provided in the second logic state if any of said plurality of comparator cells in a column provides the first output signal in the first logic state, and provided in the first logic state otherwise, and for providing the feedback signal in the second logic state if all of the first output signals are in the first logic state, wherein for all columns except the least significant column a plurality of enable carry signals of the column provides a plurality of enable input signals of a next most significant column, wherein for all columns except the most significant column the plurality of enable input signals of the column are formed by the plurality of enable carry signals of a next least significant column, and wherein the plurality of enable input signals of the most significant column are formed by a plurality of select signals.

Claim 9

A binary magnitude comparator having a plurality of rows and a plurality of columns, including a most significant column and a least significant column, comprising: a plurality of rows and columns of comparator cells, each of said plurality of comparator cells storing a data bit and comparing the stored data bit with a predetermined logic state to provide a first output signal, said data bit being in either a first logic state or a second logic state, and the first output signal being in the first logic state when an enable input signal coupled thereto is in the second logic state, and providing the first output signal in a high impedance state otherwise, and for providing an enable carry bit in the second logic state if either said stored data bit or a feedback signal are in the second logic state, and the enable input signal is in the second logic state, and otherwise providing the enable carry bit in the first logic state; and sense amplifier means, coupled to the plurality of comparator cells, for receiving the first output signal from each of said plurality of comparator cells, for providing a second output signal, a bit of said second output signal associated with each of said plurality of columns, provided in the second logic state if any of said plurality of comparator cells in a column provides the first output signal in the first logic state, and provided in the first logic state otherwise, and for providing the feedback signal in the second logic state if all of the first output signals are in the first logic state, wherein for all columns except the least significant column a plurality of enable carry signals of the column provides a plurality of enable input signals of a next most significant column, wherein for all columns except the most significant column the plurality of enable input signals of the column are formed by the plurality of enable carry signals of a next least significant column, and wherein the plurality of enable input signals of the most significant column are formed by a plurality of select signals.

Claim 10

In an array of memory cells having a plurality of rows and a plurality of columns, including a most significant column and a least significant column, wherein each memory cell is located at an intersection of one of said plurality of rows and one of said plurality of columns, a method of determining a highest binary value among at least one selected row of the plurality of rows, comprising the steps of: selecting at least one row by enabling a memory cell in the most significant column in the at least one row; comparing a stored bit in the memory cell with a first logic state; providing a first output signal for each column in the first logic state if the stored bit of any enabled memory cells in each column is in the first logic state; enabling a memory cell in a next most significant column of a corresponding row of an enabled memory cell if the stored bit of the memory cell is at the first logic value or if no enabled memory cells in the column are at the first logic value; continuing said steps of comparing a stored bit, providing a first signal, and enabling a memory cell for each column until the least significant column; and providing a plurality of second output signals, each of said plurality of second output signals associated with one of said plurality of rows, and each of said plurality of second output signals at the first logic state if a corresponding memory cell in the least significant column is enabled and a stored bit of the corresponding memory cell is in the first logic state, or if no other enabled memory cells in the least significant column are in the first logic state, and in a second logic state otherwise.

Claim 11

In an array of memory cells having a plurality of rows and a plurality of columns, including a most significant column and a least significant column, wherein each memory cell is located at an intersection of one of said plurality of rows and one of said plurality of columns, a method of determining a highest binary value among at least one selected row of the plurality of rows, comprising the steps of: selecting at least one row by enabling a memory cell in the most significant column in the at least one row; comparing a stored bit in the memory cell with a first logic state; providing a first output signal for each column in the first logic state if the stored bit of any enabled memory cells in each column is in the first logic state; enabling a memory cell in a next most significant column of a corresponding row of an enabled memory cell if the stored bit of the memory cell is at the first logic value or if no enabled memory cells in the column are at the first logic value; continuing said steps of comparing a stored bit, providing a first signal, and enabling a memory cell for each column until the least significant column; and providing a plurality of second output signals, each of said plurality of second output signals associated with one of said plurality of rows, and each of said plurality of second output signals at the first logic state if a corresponding memory cell in the least significant column is enabled and a stored bit of the corresponding memory cell is in the first logic state, or if no other enabled memory cells in the least significant column are in the first logic state, and in a second logic state otherwise.