US5003356A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Thin film transistor array
Assignee: Casio Computer Co Ltd
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Filing: 1990-04-02
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Granted: 1991-03-26
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Expires: 2010-04-02
Abstract
Abstract A TFT array having a plurality of gate lines and a plurality of drain lines formed on a transparent substrate. The gate lines intersect with the drain lines. TFT are formed at the intersections of the gate lines and the drain lines. An insulating film is formed on the drain lines and the drain electrodes of the TFTs. Pixel electrodes are formed, each overlapping the corresponding gate line and the corresponding drain line. The pixel electrode has a large area and thus, have a high opening ratio. The TFT array can, therefore, help to provide a liquid crystal display having high contrast.
Inventors
- 👤 Haruo Wakai
- 👤 Nobuyuki Yamamura
- 👤 Syunichi Sato
- 👤 Minoru Kanbara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:53
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; H10D30/6729; H10D30/674; H10D86/00; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/133357; G02F1/136; G02F1/13606; G02F1/1362; G02F1/136209; G02F1/136227; G02F1/1368
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
100 words
A TFT array comprising: a transparent insulating substrate; a plurality of gate lines formed on said transparent insulating substrate; a plurality of drain lines formed on said transparent insulating substrate and intersecting with said gate lines; thin film transistors located at the intersections of said gate lines and said drain lines, each having at least a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; an insulating film covering at least said drain electrodes and said drain lines; and a transparent electrode electrically connected to said source electrodes and overlapping said gate lines and said drain lines.
Claim 2
Dependent Claim
100 words
A TFT array comprising: a transparent insulating substrate; a plurality of gate lines formed on said transparent insulating substrate; a plurality of drain lines formed on said transparent insulating substrate and intersecting with said gate lines; thin film transistors located at the intersections of said gate lines and said drain lines, each having at least a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; an insulating film covering at least said drain electrodes and said drain lines; and a transparent electrode electrically connected to said source electrodes and overlapping said gate lines and said drain lines.
Claim 3
Dependent Claim
15 words
The TFT array according to claim 1, wherein said transparent electrode is a pixel electrode.
Claim 4
Dependent Claim
19 words
The TFT array according to claim 1, wherein said source electrodes are directly connected to said transparent electrode electrically.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-25 | 1994-09-24 | 1995-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-25 | 1998-09-24 | 1999-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-25 | 2002-09-24 | 2003-03-26 | $7700.00 | Window Closed / Lapsed |