US5008209A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device including outdiffusion from polysilicon rims
Assignee: US Philips Corp
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Filing: 1990-01-10
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Granted: 1991-04-16
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Expires: 2010-01-10
Abstract
Abstract A method of manufacturing a semiconductor device is set forth using anisotropic etching techniques, such as plasma etching and reactive ion etching to obtain interconnection patterns having accurately defined rims. Various different kinds of transistors can be manufacturing in the same semiconductor body using these techniques.
Inventors
- 👤 Johannes A. Appels
- 👤 Henricus G. R. Maas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:11
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; Y; Y10; Y10S; Y10S148/00; Y10S148/131
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
115 words
A method of manufacturing a semiconductor device of a bipolar transistor characterized in that the starting member is a semiconductor body comprising an insulating layer which is present on a surface and in which at least an opening is provided while a layer pattern is formed which extends at least as far as an edge of the opening, whereupon at least at the area of the opening a layer is provided on the semiconductor body and on the layer pattern consisting of a material which is subjected impurities in the semiconductor body determining the first conductivity type diffuse through another part of the rim into the semiconductor body in order to form an emitter zone.
Claim 2
Independent Claim
115 words
A method of manufacturing a semiconductor device of a bipolar transistor characterized in that the starting member is a semiconductor body comprising an insulating layer which is present on a surface and in which at least an opening is provided while a layer pattern is formed which extends at least as far as an edge of the opening, whereupon at least at the area of the opening a layer is provided on the semiconductor body and on the layer pattern consisting of a material which is subjected impurities in the semiconductor body determining the first conductivity type diffuse through another part of the rim into the semiconductor body in order to form an emitter zone.
Claim 3
Dependent Claim
40 words
A method as claimed in claim 1 inclusive, characterized in that at least at the area of a pn junction in the semiconductor material the layer pattern is provided with a layer of conducting material which shortcircuits the pn junction.
Claim 4
Dependent Claim
34 words
A method as claimed in claim 1, characterized in that the anisotropic etching treatment is carried out, and in that the layer to be etched is brought into contact with constituents of a plasma.
Claim 5
Independent Claim
108 words
A method of manufacturing a field effect transistor, characterized in that a semiconductor device having an interconnection pattern comprising parts of a layer of polycrystalline semiconductor material and rims of semiconductor material is subjected to an oxidation treatment, in which impurities of a first conductivity type diffuse into a semi-conductor zone of a second conductivity type opposite to the first conductivity type and thus form source and drain zones of the field effect transistor, while at the area of the side walls of the interconnection pattern oxide grows more rapidly than on the semiconductor surface in the opening in which a gate electrode is provided on the oxide.
Claim 6
Independent Claim
108 words
A method of manufacturing a field effect transistor, characterized in that a semiconductor device having an interconnection pattern comprising parts of a layer of polycrystalline semiconductor material and rims of semiconductor material is subjected to an oxidation treatment, in which impurities of a first conductivity type diffuse into a semi-conductor zone of a second conductivity type opposite to the first conductivity type and thus form source and drain zones of the field effect transistor, while at the area of the side walls of the interconnection pattern oxide grows more rapidly than on the semiconductor surface in the opening in which a gate electrode is provided on the oxide.
Claim 7
Dependent Claim
31 words
A method as claimed in claim 4, characterized in that prior to the oxidation treatment a cavity is formed in the semiconductor body between the source zone and the drain zone.
Claim 8
Dependent Claim
39 words
A method as claimed in claim 4, characterized in that at least at the area of a pn junction in the semiconductor material a layer pattern is provided with a layer of conducting material which short-circuits the pn junction.
References Cited (Backward Citations)
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US4466175A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-15 | 1994-10-15 | 1995-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-15 | 1998-10-15 | 1999-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-15 | 2002-10-15 | 2003-04-16 | $7700.00 | Window Closed / Lapsed |