Scan test apparatus for asynchronous circuitry

Claim 1

In a digital signal processing circuit jointly controlled by first and second mutually asynchronous clock signals, the improvement for enabling scan testing of said circuit, comprising: first and second scan chains of cascaded bistable elements connected to data inputs and outputs of said circuit which first and second scan chains are respectively independently controlled by said first and second clock signals; first and second test data inputs respectively connected to said first and second scan chains; and first and second result data outputs respectively connected to said first and second scan chains.

Claim 3

A method of testing a circuit having combinatory logic elements and first and second scan chains of cascaded bistable elements connected to said combinatory logic elements, and which combinatory logic elements and first and second scan chains are respectively controlled by first and second clock signals having logic levels which are changeable independent of each other, in a test cycle comprising: writing first and second stimulus sub-patterns respectively into the bistable elements of the first and second scan chains; first changing the logic level of said first clock signal, while maintaining said second clock signal at a constant logic level, for form, under the influence of said combinatory logic elements, a first response sub-pattern in said first scan chain; first reading serially the first respone sub-pattern from the first scan chain; rewriting the first stimulus sub-pattern into the bistable elements of the first scan chain; second changing the logic level of said second clock signal, while maintaining said first clock signal at a constant logic level, to form, under the influence of said combinatory logic elements, a second response sub-pattern in said second scan chain; and second reading serially the second response sub-pattern from the second scan chain.

Claim 4

A method of testing a circuit having combinatory logic elements and first and second scan chains of cascaded bistable elements connected to said combinatory logic elements, and which combinatory logic elements and first and second scan chains are respectively controlled by first and second clock signals having logic levels which are changeable independent of each other, in a test cycle comprising: writing first and second stimulus sub-patterns respectively into the bistable elements of the first and second scan chains; first changing the logic level of said first clock signal, while maintaining said second clock signal at a constant logic level, for form, under the influence of said combinatory logic elements, a first response sub-pattern in said first scan chain; first reading serially the first respone sub-pattern from the first scan chain; rewriting the first stimulus sub-pattern into the bistable elements of the first scan chain; second changing the logic level of said second clock signal, while maintaining said first clock signal at a constant logic level, to form, under the influence of said combinatory logic elements, a second response sub-pattern in said second scan chain; and second reading serially the second response sub-pattern from the second scan chain.

Claim 5

A method of testing a circuit which comprises a set of bistable elements and a set of combinatory logic elements connected thereto, according to which method a first and a second scan chain are formed, each chain consisting of a respective cascade connection of bistable elements which are controlled by a first and a second clock signal, respectively, which clock signals are mutually asynchronous, a test cycle comprising: (1) an input step during which a stimulus pattern is written into the bistable elements, a first stimulus sub-pattern being written into the first scan chain whilst a second stimulus sub-pattern is written into the second scan chain; a first test sub-cycle comprising: (2a) a processing step for the first scan chain during which a first response sub-pattern of a response pattern formed from the stimulus pattern under the influence of the combinatory logic elements is transferred to the first scan chain under the control of the first clock signal and in the absence of any other asynchronous clock signal; (2b) an output step for the first scan chain during which the first response sub-pattern is serially read; (2c) a refresh step for the first scan chain during which the first stimulus sub-pattern is refreshed; and a second test sub-cycle comprising: (3a) a processing step for the second scan chain: as the step (2a), be it that "first" is replaced by "second"; (3b) an output step for the second scan chain; as the step (2b), be it that "first" is to be replaced by "second".

Claim 6

A method of testing a circuit which comprises a set of bistable elements and a set of combinatory logic elements connected thereto, according to which method a first and a second scan chain are formed, each chain consisting of a respective cascade connection of bistable elements which are controlled by a first and a second clock signal, respectively, which clock signals are mutually asynchronous, a test cycle comprising: (1) an input step during which a stimulus pattern is written into the bistable elements, a first stimulus sub-pattern being written into the first scan chain whilst a second stimulus sub-pattern is written into the second scan chain; a first test sub-cycle comprising: (2a) a processing step for the first scan chain during which a first response sub-pattern of a response pattern formed from the stimulus pattern under the influence of the combinatory logic elements is transferred to the first scan chain under the control of the first clock signal and in the absence of any other asynchronous clock signal; (2b) an output step for the first scan chain during which the first response sub-pattern is serially read; (2c) a refresh step for the first scan chain during which the first stimulus sub-pattern is refreshed; and a second test sub-cycle comprising: (3a) a processing step for the second scan chain: as the step (2a), be it that "first" is replaced by "second"; (3b) an output step for the second scan chain; as the step (2b), be it that "first" is to be replaced by "second".