System for synchronizing data frames in a serial bit stream

Claim 1

A system for determining frame alignment within a serial data stream, each frame having a frame bit, comprising: a shift register having N bit locations, said register initially having all N bits set to a first logic state; first logic means for generating a candidate signal when selected bits from the data stream match a preselected pattern; second logic means for shifting the first logic state into said shift register if a current shift register output is in the first logic state and said first logic means is generating a candidate signal, and for shifting a second logic state into said shift register otherwise; and a modulo N counter, wherein said counter is incremented each time said second logic means shifts the second logic state into said shift register, and wherein said counter generates a signal identifying a frame bit position when it counts to (N-1), and wherein said counter is reset when the first logic state is shifted into said register by said second logic means.

Claim 2

A system for determining frame alignment within a serial data stream, each frame having a frame bit, comprising: a shift register having N bit locations, said register initially having all N bits set to a first logic state; first logic means for generating a candidate signal when selected bits from the data stream match a preselected pattern; second logic means for shifting the first logic state into said shift register if a current shift register output is in the first logic state and said first logic means is generating a candidate signal, and for shifting a second logic state into said shift register otherwise; and a modulo N counter, wherein said counter is incremented each time said second logic means shifts the second logic state into said shift register, and wherein said counter generates a signal identifying a frame bit position when it counts to (N-1), and wherein said counter is reset when the first logic state is shifted into said register by said second logic means.

Claim 8

A method for synchronizing a received serial data stream having frame bits spaced N bits apart, comprising the steps of: setting all bits of an N bit shift register to a first logic state; for each received data bit, generating a candidate signal if a plurality of spaced received bits matches a preselected pattern; for each received data bit, shifting the shift register and incrementing a modulo N counter; if a bit shifted out of the shift register is in the first logic state and a candidate signal is generated, then shifting a bit having the first logic state into the shift register and resetting the counter, otherwise shifting a bit having a second logic state into the shift register; and generating a frame synchronization signal when the counter counts to (N-1).

Claim 9

A method for synchronizing a received serial data stream having frame bits spaced N bits apart, comprising the steps of: setting all bits of an N bit shift register to a first logic state; for each received data bit, generating a candidate signal if a plurality of spaced received bits matches a preselected pattern; for each received data bit, shifting the shift register and incrementing a modulo N counter; if a bit shifted out of the shift register is in the first logic state and a candidate signal is generated, then shifting a bit having the first logic state into the shift register and resetting the counter, otherwise shifting a bit having a second logic state into the shift register; and generating a frame synchronization signal when the counter counts to (N-1).

Claim 13

A system for determining frame alignment in a received serial bit stream, comprising: a first shift register for receiving the serial bit stream, said first register having a plurality of data outputs spaced N bits apart; combinational logic circuitry connected to the data outputs for generating a candidate signal when a set of data outputs spaced K*N bits apart matches a preselected pattern; a second shift register having N bits, said second shift register initially having all N bits set to a first logic state, wherein said second shift register is shifted once as each bit in the bit stream is received; selector logic circuitry for shifting the first logic state into the second shift register if a current second shift register output is in the first logic state and said combinational logic circuitry is generating a candidate signal, and for shifting a second logic state into said second shift register otherwise; and a modulo N counter, wherein said counter is incremented each time said selector logic circuitry shifts the second logic state into said second shift register, and wherein said counter generates a frame alignment signal when it counts to (N-1), and wherein said counter is reset when the first logic state is shifted into said second shift register by said selector logic circuitry.

Claim 14

A system for determining frame alignment in a received serial bit stream, comprising: a first shift register for receiving the serial bit stream, said first register having a plurality of data outputs spaced N bits apart; combinational logic circuitry connected to the data outputs for generating a candidate signal when a set of data outputs spaced K*N bits apart matches a preselected pattern; a second shift register having N bits, said second shift register initially having all N bits set to a first logic state, wherein said second shift register is shifted once as each bit in the bit stream is received; selector logic circuitry for shifting the first logic state into the second shift register if a current second shift register output is in the first logic state and said combinational logic circuitry is generating a candidate signal, and for shifting a second logic state into said second shift register otherwise; and a modulo N counter, wherein said counter is incremented each time said selector logic circuitry shifts the second logic state into said second shift register, and wherein said counter generates a frame alignment signal when it counts to (N-1), and wherein said counter is reset when the first logic state is shifted into said second shift register by said selector logic circuitry.