US5012138A
Expired / Lapsed
US
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Interface circuit for asychronous data transfer
Assignee: Yamaha Corp
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Filing: 1989-07-25
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Granted: 1991-04-30
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Expires: 2009-07-25
Abstract
Abstract An interface circuit connected between first and second units includes first and second registers, wherein these first and second units are asynchronous with each other. Data from the first unit is written into the first register by a write pulse from the first unit, while the output of first register is to be read by the second register by a read-in pulse from the second unit. This write pulse is asynchronous with the read-in pulse. When a phase difference between phases of the write pulse and read-in pulse is within the predetermined phase range, the phase of read-in pulse is varied by the predetermined phase value, e.g., 180 degrees. Then the second register reads in the output of first register by this read-in pulse whose phase is varied. Thereafter, the output of second register is fed to the second unit, so that the data transfer is performed between the first and second units without data dropout.
Inventors
- 👤 Takashi Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:35
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0008; H04L7/0012; H04L7/0016; H04L7/0045
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
116 words
An interface circuit comprising: (a) a first register for reading in input data by a first pulse signal; (b) a second register for reading in an output of said first register by a second pulse signal which is asynchronous with said first pulse signal, wherein said second pulse signal can be arbitrarily generated at any predetermined generation timing; (c) phase difference detecting means for detecting whether or not a phase difference between phases of said first and second pulse signals is within a predetermined range; and (d) selecting means for selecting a predetermined generation timing for said second pulse signal when said phase difference detecting means detects that said phase difference is within the predetermined range.
Claim 2
Dependent Claim
116 words
An interface circuit comprising: (a) a first register for reading in input data by a first pulse signal; (b) a second register for reading in an output of said first register by a second pulse signal which is asynchronous with said first pulse signal, wherein said second pulse signal can be arbitrarily generated at any predetermined generation timing; (c) phase difference detecting means for detecting whether or not a phase difference between phases of said first and second pulse signals is within a predetermined range; and (d) selecting means for selecting a predetermined generation timing for said second pulse signal when said phase difference detecting means detects that said phase difference is within the predetermined range.
Claim 3
Dependent Claim
36 words
An interface circuit according to claim 1 wherein said selecting means changes the phase of said second pulse signal to a phase which is different from the phase of said first pulse signal by 180 degrees.
Claim 4
Dependent Claim
161 words
An interface circuit for performing a data transfer betwreen a first unit and a second unit which are asynchronous with each other comprising: (a) a first register for reading in input data from said first unit by a write pulse; (b) a second register for reading in an output of said first register by a read-in pulse from said second unit, wherein said read-in pulse is asynchronous with said write pulse; (c) phase coincidence detecting means for detecting whether or not a phase difference between phases of said write pulse and said read-in pulse is within a predetermined phase range; (d) phase changing means for changing the phase of said read-in pulse by a predetermined phase value when said phase coincidence detecting means detects that said phase difference is within the predetermined phase range; and (e) a third register for reading in an output of said second register by a timing which is different from a timing of said read-in pulse.
Claim 5
Dependent Claim
161 words
An interface circuit for performing a data transfer betwreen a first unit and a second unit which are asynchronous with each other comprising: (a) a first register for reading in input data from said first unit by a write pulse; (b) a second register for reading in an output of said first register by a read-in pulse from said second unit, wherein said read-in pulse is asynchronous with said write pulse; (c) phase coincidence detecting means for detecting whether or not a phase difference between phases of said write pulse and said read-in pulse is within a predetermined phase range; (d) phase changing means for changing the phase of said read-in pulse by a predetermined phase value when said phase coincidence detecting means detects that said phase difference is within the predetermined phase range; and (e) a third register for reading in an output of said second register by a timing which is different from a timing of said read-in pulse.
Claim 6
Dependent Claim
17 words
An interface circuit according to claim 3 wherein said predetermined phase value is equal to 180 degrees.
Claim 7
Dependent Claim
81 words
An interface circuit according to claim 3 wherein said read-in pulse includes a first read-in pulse and a second read-in pulse whose phases are different from each other by 180 degrees, one of said first read-in pulse and said second read-in pulse being selectively fed to said second register, said phase changing means changing over said first read-in pulse to said second read-in pulse when said phase coincidence detecting means detects that said phase difference is within the predetermined phase range.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-29 | 1994-10-29 | 1995-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-29 | 1998-10-29 | 1999-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-29 | 2002-10-29 | 2003-04-30 | $7700.00 | Window Closed / Lapsed |