Programmable read only memory being capable of controlling internal writing voltage of external voltage

Claim 2

A semiconductor integrated circuit device, including a nonvolatile storage element for storing information, said storage element having a first electrode for receiving a first predetermined voltage and a second electrode for receiving a second voltage, comprising: internal voltage generating means for generating an internal voltage; voltage limiting means comprising a zener diode coupled between an internal reference voltage node and said internal voltage generating means, said voltage limiting means limiting said internal voltage on the basis of a reference voltage applied to said internal reference voltage node; an external terminal; a control circuit means; first switching means coupled between said internal reference voltage node and a predetermined voltage terminal having a predetermined voltage, and responsive to said control circuit means for supplying said internal reference voltage node with said predetermined voltage; second switching means coupled between said internal reference voltage node and said external terminal, and responsive to said control circuit means for supplying said internal reference voltage node with an external voltage applied on said external terminal, whereby said control circuit means selectively limits said internal voltage by said first and second switching means in which either said predetermined voltage or said external voltage is selectively applied to said internal reference voltage node; and internal voltage providing means coupled to said voltage limiting means for supplying said second electrode with said limited internal voltage as said second voltage.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said external terminal is used for receiving an input signal and said external terminal is connected with latch means for holding said input signal.

Claim 4

A semiconductor integrated circuit device according to claim 2, wherein said nonvolatile storage element is included in an electrically writable and erasable nonvolatile memory cell, said limited internal voltage is used for electrically writing a predetermined information into said memory cell, and said input signal is an output enable signal for controlling data outputting condition.

Claim 5

A semiconductor integrated circuit device according to claim 3, wherein said control circuit means generates control signals for controlling said first and second switch means, and said control signals are generated dependent on combinations of external control signals inclusive of said output enable signal.

Claim 6

A semiconductor integrated circuit device according to claim 1, wherein said first electrode is a semiconductor region and said second electrode is a gate electrode.

Claim 7

A semiconductor integrated circuit device according to claim 5, wherein said voltage generating means includes an oscillator circuit and a voltage generating circuit responsive to output pulses of said oscillator circuit for providing said internal voltage.

Claim 8

A semiconductor, integrated circuit device according to claim 5, wherein said control means is coupled to said first and second switching means for controlling said first and second switching means so that said first and second switching means are complementarily operated from each other.

Claim 9

A semiconductor integrated circuit device according to claim 7, wherein said voltage generating means includes an oscillator circuit and a voltage generating circuit responsive to output pulses of said oscillator circuit for providing said internal voltage.

Claim 10

A semiconductor integrated circuit device according to claim 1, wherein each of said first and second switching means includes a MOSFET.

Claim 11

A semiconductor integrated circuit device including a memory element for storing an information and having a plurality of operation modes, comprising: internal voltage generating means for generating an internal voltage; voltage limiting means comprising a zener diode coupled to said voltage generating means for limiting said internal voltage on the basis of different voltages applied to said voltage limiting means; a first external terminal for receiving a first signal; a second external terminal; control means for selectively limiting said internal voltage by applying to said voltage limiting means either a predetermined internal voltage or an external voltage which is applied to said second external terminal; said control means comprising timing signal generating means coupled to said first external terminal, said timing signal generating means generating a first timing signal in response to a change of said first signal from a first level to a second level and generating a second timing signal in response to a change of said first signal from said second level to said first level; mode setting means coupled to said second external terminal and including a first holding means for holding information provided from said second external terminal in response to said first timing signal and a second holding means for holding information provided from said second external terminal in response to said second timing signal; mode defining means coupled to said mode setting means for selecting one of said operation modes on the basis of the information provided by said first and second holding means; and performing means coupled to said mode defining means and for performing said selected operation mode selected by said defining means.

Claim 12

A semiconductor integrated circuit device including a memory element for storing an information and having a plurality of operation modes, comprising: internal voltage generating means for generating an internal voltage; voltage limiting means comprising a zener diode coupled to said voltage generating means for limiting said internal voltage on the basis of different voltages applied to said voltage limiting means; a first external terminal for receiving a first signal; a second external terminal; control means for selectively limiting said internal voltage by applying to said voltage limiting means either a predetermined internal voltage or an external voltage which is applied to said second external terminal; said control means comprising timing signal generating means coupled to said first external terminal, said timing signal generating means generating a first timing signal in response to a change of said first signal from a first level to a second level and generating a second timing signal in response to a change of said first signal from said second level to said first level; mode setting means coupled to said second external terminal and including a first holding means for holding information provided from said second external terminal in response to said first timing signal and a second holding means for holding information provided from said second external terminal in response to said second timing signal; mode defining means coupled to said mode setting means for selecting one of said operation modes on the basis of the information provided by said first and second holding means; and performing means coupled to said mode defining means and for performing said selected operation mode selected by said defining means.

Claim 13

A semiconductor integrated circuit device according to claim 6, whereby one of said operation modes provides a mode for simultaneous writing of the same data into all its memory elements.

Claim 14

A semiconductor integrated circuit device according to claim 10, wherein said first external terminal receives a write enable signal for controlling writing condition, and said plurality of holding means make latching operations in synchronism with a change in said write enable signal.

Claim 15

A semiconductor integrated circuit device according to claim 12, wherein said mode defining means determines the operating conditions dependent on information latched in said plurality of said holding means and said write enable signal.

Claim 16

A semiconductor integrated circuit device according to claim 12, further comprising a timer circuit for producing timing signals which provide holding timing for said holding means dependent on said write enable signal and said timing signals being outputted after a predetermined period of time has elapsed.

Claim 17

A semiconductor integrated circuit device according to claim 14, further comprising an oscillator circuit, and a voltage generating means including a charge pump, and wherein said voltage generating means is caused to perform a charging operation by a clock signal generated by said oscillator circuit and said timer circuit perform a time counting operation by counting the clock signal generated by said oscillator circuit.

Claim 18

A semiconductor memory device including a nonvolatile storage element which requires a predetermined write voltage to write data into said nonvolatile storage element, comprising: voltage generating means for generating an internal voltage; voltage limiting means comprising a zener diode coupled between said voltage generating means and an internal reference node, said voltage limiting means limiting said internal voltage in accordance with a reference voltage applied on said internal reference node; an external terminal; control means for generating a control signal; external voltage providing means coupled to said external terminal and to said internal reference node, and including means for selectively providing an external voltage applied on said external terminal to said internal reference node; and said selectively providing means comprising switching means coupled to said internal reference node and a predetermined reference voltage terminal which provides a predetermined reference voltage, and said switching means coupled to said internal reference node and said external terminal, and responsive to said control signal from said control means for selectively providing to said internal reference node either said predetermined reference voltage so that said limited internal voltage becomes substantially equal to said predetermined write voltage or said external voltage which allows said limited internal voltage to change to a voltage having a smaller or higher absolute value than that of said predetermined write voltage on the basis of said external voltage.

Claim 19

A semiconductor memory device including a nonvolatile storage element which requires a predetermined write voltage to write data into said nonvolatile storage element, comprising: voltage generating means for generating an internal voltage; voltage limiting means comprising a zener diode coupled between said voltage generating means and an internal reference node, said voltage limiting means limiting said internal voltage in accordance with a reference voltage applied on said internal reference node; an external terminal; control means for generating a control signal; external voltage providing means coupled to said external terminal and to said internal reference node, and including means for selectively providing an external voltage applied on said external terminal to said internal reference node; and said selectively providing means comprising switching means coupled to said internal reference node and a predetermined reference voltage terminal which provides a predetermined reference voltage, and said switching means coupled to said internal reference node and said external terminal, and responsive to said control signal from said control means for selectively providing to said internal reference node either said predetermined reference voltage so that said limited internal voltage becomes substantially equal to said predetermined write voltage or said external voltage which allows said limited internal voltage to change to a voltage having a smaller or higher absolute value than that of said predetermined write voltage on the basis of said external voltage.

Claim 20

A semiconductor memory device according to claim 16, wherein said switching means includes a switching element having an input node for receiving said predetermined reference voltage, an output node coupled to said internal reference node and a control node for receiving said control signal for controlling a switch operation of said switch element.

Claim 21

A semiconductor memory device according to claim 17, wherein said switching element includes a first MOSFET having an electrode coupled to said input node, and an electrode coupled to said output node and a gate electrode coupled to said control node.

Claim 22

A semiconductor memory device according to claim 18, wherein said switching means includes a second MOSFET having an electrode coupled to said external terminal, an electrode coupled to said internal reference node and a gate electrode coupled to said control node.

Claim 23

A semiconductor memory device according to claim 16, wherein said voltage generating means includes an oscillation circuit and a voltage elevating circuit for generating said internal voltage on the basis of output signals of said oscillation circuit.

Claim 24

In a nonvolatile semiconductor memory device having first and second external terminals, a plurality of nonvolatile storage elements, and a plurality of operating modes, mode selection means for generating a mode selection signal, comprising: internal voltage generating means for generating an internal voltage; voltage limiting means comprising a zener diode coupled to said voltage generating means for limiting said internal voltage on the basis of different voltages applied to said voltage limiting means; control means for selectively limiting said internal voltage by applying to said voltage limiting means either a predetermined internal voltage or an external voltage which is applied to said second external terminal; said control means comprising timing signal generating means coupled to said first external terminal, and including means for generating a first operation signal in response to a change of a control signal applied to said first external terminal from a first level to a second level and means for generating a second operation signal in response to a change of said control signal from said second level to said first level; first holding means coupled to said second external terminal and responsive to said first operation signal for holding a data applied to said second external terminal in said first holding means; second holding means coupled to said second external terminal and responsive to said second operation signal for holding a data applied to said second external terminal in said second holding means; and mode select circuit coupled to said first and second holding means and for generating said mode selection signal on the basis of the data held in said first and second holding means.

Claim 25

In a nonvolatile semiconductor memory device having first and second external terminals, a plurality of nonvolatile storage elements, and a plurality of operating modes, mode selection means for generating a mode selection signal, comprising: internal voltage generating means for generating an internal voltage; voltage limiting means comprising a zener diode coupled to said voltage generating means for limiting said internal voltage on the basis of different voltages applied to said voltage limiting means; control means for selectively limiting said internal voltage by applying to said voltage limiting means either a predetermined internal voltage or an external voltage which is applied to said second external terminal; said control means comprising timing signal generating means coupled to said first external terminal, and including means for generating a first operation signal in response to a change of a control signal applied to said first external terminal from a first level to a second level and means for generating a second operation signal in response to a change of said control signal from said second level to said first level; first holding means coupled to said second external terminal and responsive to said first operation signal for holding a data applied to said second external terminal in said first holding means; second holding means coupled to said second external terminal and responsive to said second operation signal for holding a data applied to said second external terminal in said second holding means; and mode select circuit coupled to said first and second holding means and for generating said mode selection signal on the basis of the data held in said first and second holding means.

Claim 26

A nonvolatile semiconductor memory device according to claim 21, further comprising selection means for selecting a predetermined nonvolatile storage element from said nonvolatile storage elements, read out means coupled to said selected nonvolatile storage element and for reading out a data from said selected storage element, and an external terminal for receiving said read out data.

Claim 27

A nonvolatile semiconductor memory device according to claim 22, further comprising writing means coupled to said selected nonvolatile storage element and responsive to a writing control signal for writing a predetermined data into said selected storage element, wherein said writing control signal is generated in accordance with an external control signal supplied to said first external terminal and an output control signal for controlling said read out means is generated in accordance with an external control signal supplied to said second external terminal.

Claim 28

A semiconductor memory device including a plurality of nonvolatile storage elements each of which requires a predetermined voltage to write a data into a nonvolatile storage element, a first external terminal for receiving an external writing control signal and a second external terminal for receiving an external output control signal for controlling output of a stored data in a nonvolatile storage element, said semiconductor memory device comprising: voltage generating means for generating a first voltage; voltage limiting means coupled to said voltage generating means and including an internal reference node and means for limiting said first voltage to a limited voltage in accordance with a second voltage applied to said internal reference node; external voltage providing means coupled to said first external terminal and to said internal reference node, and including means for providing an internal voltage corresponding to an external voltage applied to said second external terminal to said internal reference node; switching means coupled to said internal reference node and to mode selection means and responsive to a mode selection signal from said mode selection means for providing a reference voltage to said internal reference node so that said limited voltage becomes substantially equal to said predetermined voltage, wherein said switching means allows said limited voltage to change to a voltage having smaller absolute value than that of said predetermined voltage in accordance with said external voltage in a state which said switching means does not provide said reference voltage to said internal reference node; and said mode selection means including: timing signal generating means coupled to said first external terminal, and including means responsive to a change from a first level to a second level in a control signal to be applied to said first external terminal for generating a first operation signal and means responsive to a change from said second level to said first level in said control signal for generating a second operation signal; first holding means coupled to said second external terminal and responsive to said first operation signal for holding data applied on said second external terminal; second holding means coupled to said second external terminal and responsive to said second operations signal for holding data applied on said second external terminal; and mode select circuit coupled to said first and second holding means and for generating said mode selection signal in accordance with the held data in said first and second holding means.

Claim 29

A semiconductor memory device including a plurality of nonvolatile storage elements each of which requires a predetermined voltage to write a data into a nonvolatile storage element, a first external terminal for receiving an external writing control signal and a second external terminal for receiving an external output control signal for controlling output of a stored data in a nonvolatile storage element, said semiconductor memory device comprising: voltage generating means for generating a first voltage; voltage limiting means coupled to said voltage generating means and including an internal reference node and means for limiting said first voltage to a limited voltage in accordance with a second voltage applied to said internal reference node; external voltage providing means coupled to said first external terminal and to said internal reference node, and including means for providing an internal voltage corresponding to an external voltage applied to said second external terminal to said internal reference node; switching means coupled to said internal reference node and to mode selection means and responsive to a mode selection signal from said mode selection means for providing a reference voltage to said internal reference node so that said limited voltage becomes substantially equal to said predetermined voltage, wherein said switching means allows said limited voltage to change to a voltage having smaller absolute value than that of said predetermined voltage in accordance with said external voltage in a state which said switching means does not provide said reference voltage to said internal reference node; and said mode selection means including: timing signal generating means coupled to said first external terminal, and including means responsive to a change from a first level to a second level in a control signal to be applied to said first external terminal for generating a first operation signal and means responsive to a change from said second level to said first level in said control signal for generating a second operation signal; first holding means coupled to said second external terminal and responsive to said first operation signal for holding data applied on said second external terminal; second holding means coupled to said second external terminal and responsive to said second operations signal for holding data applied on said second external terminal; and mode select circuit coupled to said first and second holding means and for generating said mode selection signal in accordance with the held data in said first and second holding means.