US5013385A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Quad processor
Assignee: Applied Materials Inc
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Filing: 1989-12-01
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Granted: 1991-05-07
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Expires: 2009-12-01
Abstract
Abstract The present invention includes plural plasma etching vessels and a wafer queuing station arrayed with a wafer transfer arm in a controlled environment. Wafers are movable within the controlled environment one at a time selectably between the several plasma vessels and the wafer queuing station without atmospheric or other exposure to that possible contamination of the moved wafers is prevented. The system is selectively operative in either single-step or multiple-step processing modes, and in either of the modes, the several plasma etching vessels are operable to provide a desirably high system throughput. In the preferred embodiment, the several plasma vessels and the queuing station are arrayed about a closed pentagonal locus with the wafer transfer arm disposed within the closed locus. Wafer processing in each vessel is regulated by a state controller for processing a plurality of wafers from a single cassette, contained within the vacuum environment of the plural plasma etching vessels and wafer queuing station, to provide an orderly and efficient throughput of wafers for diverse or similar processing in the plural vessels. In this manner a wafer can be processed as soon as a vessel becomes available.
Inventors
- 👤 Joseph A. Maher
- 👤 E. John Vowles
- 👤 Joseph D. Napoli
- 👤 Arthur W. Zafiropoulo
- 👤 Mark W. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:37
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/04; H10P72/0451; H10P72/0462; H01; H01J; H01J37/00; H01J37/02; H01J37/18; H01J37/185; H10P72/0441; H10P72/0464; H10P72/30; H10P72/33; H10P72/3302; Y; Y10; Y10S; Y10S414/00; Y10S414/135; Y10S414/141
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
192 words
A multiple-processing and contamination-free wafer handling and processing system, comprising: plural, wafer receiving and surface processing vessels each having an ingress and egress defining port that are arrayed about a predetermined spacial locus in such a way that the several ports thereof are accessible from a single location spaced from the several ports; a wafer queuing station spaced with the plural vessels along the same predetermined spacial locus defining a wafer access port accessible from said single location; plural valve means individually coupled to corresponding ones of said plural, vessel ingress and egress ports and to said wafer queuing station wafer access port; transfer means disposed at said single location and cooperative with corresponding ones of said plural valve means for moving wafers from and to said wafer access port of said queuing station from and to selected ones of said wafer receiving and surface processing vessels through the associated one of said ingress and egress ports thereof; and processor means for controlling said vessels, said transfer means and said valve means to provide selectable single or multistep processing of wafers in said queuing station in one or more of said vessels.
Claim 2
Dependent Claim
192 words
A multiple-processing and contamination-free wafer handling and processing system, comprising: plural, wafer receiving and surface processing vessels each having an ingress and egress defining port that are arrayed about a predetermined spacial locus in such a way that the several ports thereof are accessible from a single location spaced from the several ports; a wafer queuing station spaced with the plural vessels along the same predetermined spacial locus defining a wafer access port accessible from said single location; plural valve means individually coupled to corresponding ones of said plural, vessel ingress and egress ports and to said wafer queuing station wafer access port; transfer means disposed at said single location and cooperative with corresponding ones of said plural valve means for moving wafers from and to said wafer access port of said queuing station from and to selected ones of said wafer receiving and surface processing vessels through the associated one of said ingress and egress ports thereof; and processor means for controlling said vessels, said transfer means and said valve means to provide selectable single or multistep processing of wafers in said queuing station in one or more of said vessels.
Claim 3
Dependent Claim
28 words
The system of claim 1, wherein said predetermined spacial locus is a closed locus, and wherein said single location coincides with the geometric center of said closed locus.
Claim 4
Dependent Claim
26 words
The system of claim 1, wherein said wafer queuing station includes a cassette and an indexing elevator mechanism for moving said cassette in the vertical direction.
Claim 5
Dependent Claim
17 words
The system of claim 1, wherein each of said vessels include walls defining a plasma etching chamber.
Claim 6
Dependent Claim
36 words
The system of claim 4, wherein each of said plural plasma etching vessels further include first and second electrodes, and means for mounting said first and said second electrodes to said walls for relative electrode motion.
Claim 7
Dependent Claim
39 words
The system of claim 5, wherein each of said plural plasma etching vessels further include a pedestal inset into one of said electrodes, and means for mounting said pedestal for vertical motion relative to said one of said electrodes.
Claim 8
Dependent Claim
25 words
The system of claim 5, wherein each of said plural plasma etching vessels further include means for cooling/heating said first and said second electrodes thereof.
Claim 9
Dependent Claim
46 words
The system of claim 1, wherein said wafer transfer means includes a wafer receiving arm, and means mounted to the arm for picking-up single wafers by contacting their periphery and in such a way that no contact is made of the front surface of the wafer.
Claim 10
Dependent Claim
49 words
The system of claim 2, wherein said wafer transfer means includes an R, TT moveable wafer receiving arm having means for picking-up single wafers disposed on said arm by contacting their periphery and in such a way that no contact is made of the front surface of the wafers.
Claim 11
Dependent Claim
51 words
The system of claim 9, wherein said R, TT moveable wafer receiving arm assembly includes a base member platform and means for rotating said base member platform in TT about an axis; a paddle; and means for mounting said paddle for sliding motion in R relative to said base member platform.
Claim 12
Dependent Claim
35 words
The system of claim 10, wherein said paddle includes a wafer supporting first portion, a wafer edge engaging second portion, and means for mounting said second portion for sliding motion relative to said first portion.
Claim 13
Dependent Claim
54 words
The system of claim 11, wherein said first portion of said paddle has an upstanding abutment on an edge thereof and wherein said wafer edge engaging second portion includes a slide having a bumper that cooperates with said upstanding abutment of said first portion to engage the periphery of a single wafer disposed therebetween.
Claim 14
Dependent Claim
19 words
The system of claim 12, wherein said paddle further includes means for resiliently urging said bumper towards said abutment.
Claim 15
Dependent Claim
20 words
The system of claim 13, further including means for sensing whether or not the wafer is seated on the platform.
Claim 16
Dependent Claim
16 words
The system of claim 14, wherein said sensing means includes contact-responsive switches mounted to the platform.
Claim 17
Dependent Claim
23 words
The system of claim 1, wherein each of the plural wafer receiving and surface processing vessels includes a low-frequency plasma discharge producing source.
Claim 18
Dependent Claim
23 words
The system of claim 1, wherein each of the plural wafer receiving and surface processing vessels includes a high-frequency plasma discharge producing source.
Claim 19
Dependent Claim
23 words
The system of claim 1, wherein each of the plural wafer receiving and surface processing vessels includes a microwave-frequency plasma discharge producing source.
Claim 20
Dependent Claim
19 words
The system of claim 16, wherein the low-frequency plasmas are produced at frequencies approximately of 4 to 450 khz.
Claim 21
Dependent Claim
19 words
The system of claim 17, wherein the high-frequency plasmas are produced at frequencies approximately of 1 to 50 mhz.
Claim 22
Dependent Claim
18 words
The system of claim 18, wherein the microwave-frequency plasmas are produced at frequencies approximately 1 to 4 GHz.
Claim 23
Dependent Claim
13 words
The system of claim 5, wherein said electrodes are in a diode configuration.
Claim 24
Dependent Claim
13 words
The system of claim 5 wherein said electrodes are in a triode configuration.
Claim 25
Dependent Claim
13 words
The system of claim 5, further including means for magnetically enhancing said electrodes.
Claim 26
Independent Claim
167 words
A system for providing semiconductor wafer processing of a plurality of semiconductor wafers contained in a cassette in conjunction with a plurality of wafer receiving and surface processing chambers comprising: an array of wafer stations comprising: at least one wafer cassette queuing station adapted for containing a plurality of wafers in individual slots of a wafer containment cassette; a plurality of wafer receiving and surface processing vessels; means for providing gated entrance to said wafer receiving and surface processing vessels to provide in a first state sealed containment of an environment within each of said vessels and in a second state access to the vessel interior; means for transporting wafers between selected slots in a cassette at said queuing station and the interior of selected vessels via said gated entrance means in said second state; processor means for sequencing wafers between associated slot positions in a cassette of said queuing stations and one or more of said vessels in accordance with processing commands associated with each wafer.
Claim 27
Independent Claim
167 words
A system for providing semiconductor wafer processing of a plurality of semiconductor wafers contained in a cassette in conjunction with a plurality of wafer receiving and surface processing chambers comprising: an array of wafer stations comprising: at least one wafer cassette queuing station adapted for containing a plurality of wafers in individual slots of a wafer containment cassette; a plurality of wafer receiving and surface processing vessels; means for providing gated entrance to said wafer receiving and surface processing vessels to provide in a first state sealed containment of an environment within each of said vessels and in a second state access to the vessel interior; means for transporting wafers between selected slots in a cassette at said queuing station and the interior of selected vessels via said gated entrance means in said second state; processor means for sequencing wafers between associated slot positions in a cassette of said queuing stations and one or more of said vessels in accordance with processing commands associated with each wafer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-06 | 1994-11-05 | 1995-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-06 | 1998-11-05 | 1999-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-06 | 2002-11-05 | 2003-05-07 | $7700.00 | Window Closed / Lapsed |