US5014190A
Expired / Lapsed
US
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Data processing system
Assignee: QED INTELLECTUAL PROPERTY SERVICES Ltd
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Filing: 1987-11-02
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Granted: 1991-05-07
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Expires: 2007-11-02
Abstract
Abstract A data processing system includes a microcomputer (1) and a watchdog circuit arrangement which includes a clocked counter (17) having an output Q n which is coupled to a reset input (RST) of the microcomputer. In order to increase the kinds of microcomputer malfunctions to which the watchdog circuit responds, the microcomputer is programmed to repeatedly generate predetermined reset signal bytes within respective time windows, such time windows corresponding to periods during which a further output Q n-1 of the counter is logic "1". The reset signal byte supplied by the microcomputer is compared by a comparator (10) with the predetermined reset signal byte, which is supplied thereto by a switched multiplexor (13), and if they match the output signal from the comparator resets the counter. Each time this occurs the microcomputer strobes the watchdog circuit by applying its address to a further input (22, 46) thereof. If a reset signal byte should be supplied by the microcomputer outside a time window and/or if such signal byte is incorrect, the resulting signal level at the output of the comparator, which is stored in a flip-flop (15), actuates the watchdog circuit to produce an output signal which resets the microcomputer. The logic value of the Q n-1 signal from the counter is periodically ascertained by the microcomputer to determine the subsequent time window during which the next reset signal byte is to be generated.
Inventors
- 👤 Nigel L. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 07:55
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0763; G06F11/0754; G06F11/0757
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
195 words
A digital data processing system comprising: (a) a watch-dog circuit, which circuit comprises: (i) timer means; and (ii) a reset signal input coupled to the timer means; said watch-dog circuit generating: (iii) an output signal when (A) a time interval between successive resets of said timer means exceed a predetermined length; or (B) a reset signal is supplied to said reset signal input while a further signal is absent; and (iv) the further signal, at time intervals which do not exceed said predetermined length; and (b) a system program for: (i) supplying a reset signal to said reset signal input, and thereby resetting the timer means, during each occurrence of said further signal; and (ii) responding to said output signal by assuming a predetermined state, wherein said system is further for: (iii) periodically testing for the presence of said further signal, (iv) responding to such presence being detected by supplying a reset signal to said reset signal input while said further signal is still present, and (v) performing program steps unrelated to the watchdog circuit between each detection of the presence of said further signal and the subsequent supply of the reset signal in response.
Claim 2
Dependent Claim
195 words
A digital data processing system comprising: (a) a watch-dog circuit, which circuit comprises: (i) timer means; and (ii) a reset signal input coupled to the timer means; said watch-dog circuit generating: (iii) an output signal when (A) a time interval between successive resets of said timer means exceed a predetermined length; or (B) a reset signal is supplied to said reset signal input while a further signal is absent; and (iv) the further signal, at time intervals which do not exceed said predetermined length; and (b) a system program for: (i) supplying a reset signal to said reset signal input, and thereby resetting the timer means, during each occurrence of said further signal; and (ii) responding to said output signal by assuming a predetermined state, wherein said system is further for: (iii) periodically testing for the presence of said further signal, (iv) responding to such presence being detected by supplying a reset signal to said reset signal input while said further signal is still present, and (v) performing program steps unrelated to the watchdog circuit between each detection of the presence of said further signal and the subsequent supply of the reset signal in response.
Claim 3
Dependent Claim
195 words
A programmed digital data processing system comprising: (a) a watchdog circuit including (i) resettable timer means; (ii) a reset signal input for receiving successive reset signals to reset the timer means; and (iii) means for supplying an output signal when a time interval between successive reset signals exceeds a predetermined length; and (iv) means for supplying a further signal at intervals which do not exceed said predetermined length, the output signal supplying means also supplying the output signal when the reset signal input receives a reset signal while the further signal is absent; (b) means for periodically testing for the further signal; (c) means, responsive to the periodically testing means, for subsequently supplying a corresponding one of the successive reset signals while the further signal is still present, which corresponding one of the successive reset signals corresponds to a finding by the periodically testing means that the further signal is still present; (d) means for assuming a predetermined state in response to the output signal; and (e) means for enabling performance of program steps unrelated to the watchdog circuit between each detection of said further signal and the corresponding subsequent supply of a reset signal.
Claim 4
Dependent Claim
195 words
A programmed digital data processing system comprising: (a) a watchdog circuit including (i) resettable timer means; (ii) a reset signal input for receiving successive reset signals to reset the timer means; and (iii) means for supplying an output signal when a time interval between successive reset signals exceeds a predetermined length; and (iv) means for supplying a further signal at intervals which do not exceed said predetermined length, the output signal supplying means also supplying the output signal when the reset signal input receives a reset signal while the further signal is absent; (b) means for periodically testing for the further signal; (c) means, responsive to the periodically testing means, for subsequently supplying a corresponding one of the successive reset signals while the further signal is still present, which corresponding one of the successive reset signals corresponds to a finding by the periodically testing means that the further signal is still present; (d) means for assuming a predetermined state in response to the output signal; and (e) means for enabling performance of program steps unrelated to the watchdog circuit between each detection of said further signal and the corresponding subsequent supply of a reset signal.
Claim 5
Dependent Claim
51 words
A system as claimed in claim 2, wherein (a) each said reset signal is supplied in the form of a multibit word having a predetermined value, and (b) said circuit additionally generates said output signal when a reset signal supplied to the reset signal input does not have the predetermined value.
Claim 6
Dependent Claim
22 words
A system as claimed in claim 3, wherein the predetermined value changes for successive reset signals in accordance with a cyclic sequence.
Claim 7
Dependent Claim
25 words
A system as claimed in claim 4, wherein the sequence consists of two predetermined values each of which is a complemented version of the other.
Claim 8
Dependent Claim
35 words
A system as claimed in claim 5, further comprising a random access memory for storing the multibit word, from which random access memory the multibit word is read and rewritten for each said reset signal.
Claim 9
Dependent Claim
22 words
As system as claimed in claim 6, wherein said multibit word is complemented during each interval between supply of successive reset signals.
Claim 10
Dependent Claim
29 words
A system as claimed in claim 7, wherein each such complementing operation is separated in time from each reset signal supply operation by program steps of a system program.
Claim 11
Dependent Claim
20 words
A system as claimed in claim 5, wherein each multibit word is a byte consisting of alternate "0"s and "1"s.
Claim 12
Dependent Claim
35 words
A system as claimed in claim 3, further comprising a random access memory for storing the multibit word, from which random access memory the multibit word is read and rewritten for each said reset signal.
Claim 13
Dependent Claim
67 words
A system as claimed in claim 2, wherein instances of the further signal and the corresponding reset signals occur in an alternating series in which each further signal is present during a respective interval of time, the start of each interval during which the further signal is present having a predetermined delay with respect to the instant of occurence of the reset signal which immediately precedes it.
Claim 14
Dependent Claim
63 words
A system as claimed in claim 11, wherein (a) the timer means comprises a binary counter having a clock input and a reset input coupled to the reset signal input, said further signal being derived from a particular bit position or positions of the contents of the counter; and (b) the system further comprising clock pulse means for continuously clocking the binary counter.
Claim 15
Dependent Claim
27 words
A system as claimed in claim 2, further comprising means for strobing the watchdog circuit each time a reset signal is supplied to the reset signal input.
Claim 16
Dependent Claim
31 words
A system as claimed in claim 2, comprising a programmed microcomputer provided with an external address latch, the address latch and the watch-dog circuit being integrated on the same semiconductor chip.
Claim 17
Independent Claim
195 words
A method for using a watchdog circuit, the method comprising the steps of: (a) initializing first and second flags (F1, F2) and a specific address (AD) of a RAM to respective initialized values; (b) executing program steps unrelated to the watchdog circuit; (c) testing whether an (n-1)th bit of an n-bit counter has reached a predetermined logic level; (d) changing the first flag to a respective changed value, upon a positive result of step (c); (e) executing further program steps unrelated to the watchdog circuit; (f) testing whether the first flag has the respective changed value of step (d); (g) upon a positive result of step (f): (I) writing contents of the specific address to the watchdog circuit; (II) setting the first flag back to the respective initialized value; and (III) setting the second flag to a respective changed value; (h) executing still further program steps unrelated to the watchdog circuit; (i) testing whether the second flag has the respective changed value of step (g) (III); and (j) upon a positive result of step (i): (I) complementing the contents of the specific address; and (II) setting the second flag back to the respective initial value.
Claim 18
Independent Claim
195 words
A method for using a watchdog circuit, the method comprising the steps of: (a) initializing first and second flags (F1, F2) and a specific address (AD) of a RAM to respective initialized values; (b) executing program steps unrelated to the watchdog circuit; (c) testing whether an (n-1)th bit of an n-bit counter has reached a predetermined logic level; (d) changing the first flag to a respective changed value, upon a positive result of step (c); (e) executing further program steps unrelated to the watchdog circuit; (f) testing whether the first flag has the respective changed value of step (d); (g) upon a positive result of step (f): (I) writing contents of the specific address to the watchdog circuit; (II) setting the first flag back to the respective initialized value; and (III) setting the second flag to a respective changed value; (h) executing still further program steps unrelated to the watchdog circuit; (i) testing whether the second flag has the respective changed value of step (g) (III); and (j) upon a positive result of step (i): (I) complementing the contents of the specific address; and (II) setting the second flag back to the respective initial value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-06 | 1994-11-05 | 1995-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-06 | 1998-11-05 | 1999-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-06 | 2002-11-05 | 2003-05-07 | $7700.00 | Window Closed / Lapsed |