US5014236A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input/output bus expansion interface
Assignee: International Business Machines Corp
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Filing: 1988-01-29
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Granted: 1991-05-07
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Expires: 2008-01-29
Abstract
Abstract An I/O bus expansion interface is disclosed which enables an I/O device having an n-bit data bus to be interfaced to an m times n-bit I/O data bus of a host processor. This I/O bus expansion circuit maximizes the computer processor's performance by providing full I/O data bus bandwidth and allowing overlap of processor execution and I/O bus expansion interface circuit operation. This is accomplished by: (1) prefetching multiple control and/or data fields from the I/O device and presenting that information to the host without delay and (2) burst writing multiple fields from the host to the bus expansion interface circuit, without delay of the host, and thereafter making these fields individually available to the I/O device.
Inventors
- 👤 James S. Pogorzelski
- 👤 Craig H. Shempert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:20
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
182 words
An interface for communication between an I/O device connected to an n-bit I/O data bus and a processor connected to an m times n-bit processor I/O data bus, comprising: first register means for temporarily storing a group of fields of information, said information including at least one control field from said I/O device; and control logic means for (a) fetching said at least one control field from said I/O device, (b) decoding the content of said at least one control field, (c) fetching, a field at a time, a particular group of said fields of said information responsive to the result of said decoding the content of said at least one control field from said I/O device on said n-bit I/O data bus, (d) storing said particular group of fields of said information in said first register means including said at least one control field and (e) allowing simultaneous access to said particular group of fetched field stored in said first register means on said m times n-bit processor I/O data bus in a single m times n-bit read by said processor.
Claim 2
Dependent Claim
182 words
An interface for communication between an I/O device connected to an n-bit I/O data bus and a processor connected to an m times n-bit processor I/O data bus, comprising: first register means for temporarily storing a group of fields of information, said information including at least one control field from said I/O device; and control logic means for (a) fetching said at least one control field from said I/O device, (b) decoding the content of said at least one control field, (c) fetching, a field at a time, a particular group of said fields of said information responsive to the result of said decoding the content of said at least one control field from said I/O device on said n-bit I/O data bus, (d) storing said particular group of fields of said information in said first register means including said at least one control field and (e) allowing simultaneous access to said particular group of fetched field stored in said first register means on said m times n-bit processor I/O data bus in a single m times n-bit read by said processor.
Claim 3
Dependent Claim
51 words
The interface circuit of claim 1, wherein said control logic means further comprises means for (f) detecting a read or write request from said processor; and (g) suspending any fetching from said I/O device of said particular group of said fields following said detecting said read request or said write request.
Claim 4
Dependent Claim
38 words
The interface circuit of claim 2, wherein said control logic means further comprises means for (h) resuming any fetching from said I/O device of said particular group of said fields following completion of a read or write request.
Claim 5
Dependent Claim
35 words
The interface circuit of claim 3, wherein said control logic means further comprises means for (i) generating an interrupt directed to said processor upon completion of said fetching of said particular group of said fields.
Claim 6
Dependent Claim
58 words
The interface circuit of claim 1, wherein said control logic means further comprises: (j) means for generating an interrupt directed to said processor upon completion of said storing said at least one control field; and means responsive to said means for generating said interrupt directed to said processor for allowing access to said control field by said processor.
Claim 7
Independent Claim
168 words
A method for communicating information between an I/O device connected to an n-bit I/O data bus and a processor connected to an n-bit I/O data bus and a processor connected to an m times n-bit processor I/O data bus, said information including at least one control field from said I/O device, said method comprising: fetching said at least one control field from said I/O device; decoding the content of said at least one control field; fetching, a field at a time, a particular group of said fields of said information responsive to the result of decoding the content of said at least one control field from said I/O device on said n-bit I/O data bus; storing said particular group of fields of said information, including said at least one control field, in a register; and allowing simultaneous access to said particular group of fetched fields stored in said register on said m times n-bit processor I/O data bus in a single m times n-bit read by said processor.
Claim 8
Independent Claim
168 words
A method for communicating information between an I/O device connected to an n-bit I/O data bus and a processor connected to an n-bit I/O data bus and a processor connected to an m times n-bit processor I/O data bus, said information including at least one control field from said I/O device, said method comprising: fetching said at least one control field from said I/O device; decoding the content of said at least one control field; fetching, a field at a time, a particular group of said fields of said information responsive to the result of decoding the content of said at least one control field from said I/O device on said n-bit I/O data bus; storing said particular group of fields of said information, including said at least one control field, in a register; and allowing simultaneous access to said particular group of fetched fields stored in said register on said m times n-bit processor I/O data bus in a single m times n-bit read by said processor.
Claim 9
Dependent Claim
44 words
The method for communicating information of claim 6, further comprising detecting a read or write request from said processor and suspending any fetching from said I/O device of said particular group of said fields following said detecting said read request or said write request.
Claim 10
Dependent Claim
32 words
The method for communicating information of claim 7, further comprising resuming any fetching from said I/O device of said particular group of said fields following completion of a read or write request.
Claim 11
Dependent Claim
29 words
The method for communicating information of claim 8, further comprising generating an interrupt directed to said processor upon completion of said fetching of said particular group of said fields.
Claim 12
Dependent Claim
39 words
The method for communicating information of claim 6, further comprising: generating an interrupt directed to said processor upon completion of said storing said at least one control field; and thereafter allowing access to said control field by said processor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-06 | 1994-11-05 | 1995-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-06 | 1998-11-05 | 1999-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-06 | 2002-11-05 | 2003-05-07 | $7700.00 | Window Closed / Lapsed |