Patent DE822877C successfully refreshed from Google Patents.
US5016218A
Expired / Lapsed
US
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Nonvolatile memory with data write circuitry to reduce write errors
Assignee: Toshiba Corp
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Filing: 1988-11-21
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Granted: 1991-05-14
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Expires: 2008-11-21
Abstract
Abstract In a nonvolatile memory of the present invention, a write circuit is connected between bit lines and a write-enable voltage terminal and has at least two write MOS transistors connected to each other in a serial manner. Since at least two write MOS transistors are connected in a serial manner, a punch-through effect is reduced even if noises occur in a write voltage system. Even in the case where a punch-through effect occurs due to the presence of a power source and transistors, a voltage on the bit line is reduced, thus preventing a write error from occurring relative to the memory cell transistors.
Inventors
- 👤 Akihiro Yamazaki
- 👤 Katsuya Kiyohara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:54
CPC Classifications
H; H01; H01J; H01J29/00; H01J29/46; H01J29/70; H01J29/72; H01J29/76; G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
172 words
A nonvolatile memory comprising: bit lines connected to drains of corresponding memory cell transistors; a data write circuit, connected to each of the bit lines and to a write voltage terminal, including: a plurality of MOS transistors connected in series between said bit lines and said write voltage terminal, each of said plurality of MOS transistors having a gate; a single MOS transistor, connected to a junction between two of said plurality of serially connected MOS transistors and to a ground terminal, for supplying a current from said junction to said ground terminal; a write-enable signal line, connected to each of said gates of said plurality of serially connected MOS transistors, for applying write-enable signals to said gates; and wherein said single MOS transistor connected to said ground terminal is turned off when said plurality of serially connected MOS transistors are in an ON state, and turned on when said plurality of serially connected MOS transistors are in an OFF state, in accordance with a write-enable signal on said write-enable signal line.
Claim 2
Dependent Claim
172 words
A nonvolatile memory comprising: bit lines connected to drains of corresponding memory cell transistors; a data write circuit, connected to each of the bit lines and to a write voltage terminal, including: a plurality of MOS transistors connected in series between said bit lines and said write voltage terminal, each of said plurality of MOS transistors having a gate; a single MOS transistor, connected to a junction between two of said plurality of serially connected MOS transistors and to a ground terminal, for supplying a current from said junction to said ground terminal; a write-enable signal line, connected to each of said gates of said plurality of serially connected MOS transistors, for applying write-enable signals to said gates; and wherein said single MOS transistor connected to said ground terminal is turned off when said plurality of serially connected MOS transistors are in an ON state, and turned on when said plurality of serially connected MOS transistors are in an OFF state, in accordance with a write-enable signal on said write-enable signal line.
Claim 3
Dependent Claim
37 words
The nonvolatile memory according to claim 1, wherein a signal on said write-enable signal line is supplied, as an inverted replica, via an inverter to a gate of said single MOS transistor connected to said ground terminal.
Claim 4
Dependent Claim
171 words
A nonvolatile memory comprising: bit lines connected to drains of corresponding memory cell transistors; a data write circuit, connected to each of the bit lines and to a write voltage terminal, including: a plurality of MOs transistors connected in series between said bit lines and said write voltage terminal, each of said plurality of MOS transistors having a gate; and a single MOS transistor, connected to a junction between two of said plurality of series-connected MOS transistors and to a ground terminal, for supplying a current from said junction to the ground terminal; a write-enable signal line, connected to each of said gates of said plurality of series-connected MOS transistors, for applying write-enable signals to said gates; and wherein said single MOS transistor is turned to an OFF state when said plurality of series-connected MOS transistors are in an ON state, and is turned to an ON state when said plurality of series-connected MOS transistors are in an OFF state, in accordance with a write-enable signal on said write-enable signal line.
Claim 5
Dependent Claim
171 words
A nonvolatile memory comprising: bit lines connected to drains of corresponding memory cell transistors; a data write circuit, connected to each of the bit lines and to a write voltage terminal, including: a plurality of MOs transistors connected in series between said bit lines and said write voltage terminal, each of said plurality of MOS transistors having a gate; and a single MOS transistor, connected to a junction between two of said plurality of series-connected MOS transistors and to a ground terminal, for supplying a current from said junction to the ground terminal; a write-enable signal line, connected to each of said gates of said plurality of series-connected MOS transistors, for applying write-enable signals to said gates; and wherein said single MOS transistor is turned to an OFF state when said plurality of series-connected MOS transistors are in an ON state, and is turned to an ON state when said plurality of series-connected MOS transistors are in an OFF state, in accordance with a write-enable signal on said write-enable signal line.
Claim 6
Dependent Claim
37 words
The nonvolatile memory according to claim 3, wherein a signal on said write-enable signal line is supplied, as an inverted replica, via an inverter to a gate of said single MOS transistor connected to said ground terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-13 | 1994-11-12 | 1995-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-13 | 1998-11-12 | 1999-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-13 | 2002-11-12 | 2003-05-14 | $7700.00 | Window Closed / Lapsed |