Digital modulator and demodulator

Claim 2

A digital modulator for converting an input data train to a coded data train, comprising: grouping means for separating the input data train into data words each being composed of M bits; encoding means for converting each of the data words into a corresponding one of a plurality of code words each being composed of N bits, where N>M, and each containing a specific number of `1` bits, said plurality of code words being classified into at least two groups such that the number of `1` bits contained in each code word in each of said groups is the same and such that the number of `1` bits contained in each code word in one of said groups is different by at least 3 from the number of `1` bits contained in each code word in another of said groups; and transmitting means for transmitting the code word outputted from the encoding means in the form of a serial channel code.

Claim 3

A digital modulator as defined in claim 1 wherein M is 8, N is 10, and the number of `1` bits contained in the code word is 2 or 5.

Claim 4

A digital modulator as defined in claim 2, wherein `1` bits in a code word having two `1` bits are adjoined to each other.

Claim 5

A digital modulator as defined in claim 1 wherein M is 8, N is 10, and the number of `1` bits contained in the code word is 5 or 8.

Claim 6

A digital modulator as defined in claim 1, wherein M is 8, N is 10, and the number of `1` bits contained in the code word is 2, 5 or 8; and wherein said encoding means converts some of the data words each to one of a code word having two `1` bits and a code word having eight `1` bits so as to reduce the DC component of the channel code, and converts the remaining data words each to a code word having five `1` bits.

Claim 7

A digital modulator as defined in claim 5, wherein `1` bits in a code word having two `1` bits are adjoined to each other while `0` bits in a code word having eight `1` bits are adjoined to each other.

Claim 8

A digital modulator as defined in claim 1, wherein M is 8, N is 10, and the number of `1` bits contained in the code word is 1, 5 or 9; and wherein said encoding means converts some of the data words each to one of a code word having one `1` bit and a code word having nine `1` bits so as to reduce the DC component of the channel code, and converts the remaining data words each to a code word having five `1` bits.

Claim 9

A digital modulator as defined in claim 1, wherein M is 8, N is 10, and said encoding means converts a data word which contains 3, 4 or 5 `1` bits into a code word by adding additional 2 bits to a specific position thereof, the additional 2 bits being designated as `1` and `1` when the data word contains 3 `1` bits, `1` and `0` when the data word contains 4 `1` bits, and `0` and `0` when the data word contains 5 `1` bits.

Claim 10

A demodulator for reproducing data words each being composed of M bits from a channel signal formed of a serial train of code words each being composed of N bits, where N>M, and containing a specific number of `1` bits, said code words being classified into at least two groups such that the number of `1` bits contained in each code word in each of said groups is the same and such that the number of `1` bits contained in each code word in the number of `1` bits contained in each code word in another of said groups, comprising: a plurality of voltage comparating means having different thresholds from one another for waveform shaping the channel signal with the respective thresholds; a plurality of counting means which are respectively coupled to the plurality of voltage comparating means and each of which is for separating an output of a corresponding one of the plurality of voltage comparating means into N-bit words and counting the number of `1` bits contained in each N-bit word; maximum likelihood detecting means for identifying as a code word one having a maximum likelihood from N-bit words in each of which the number counted by the counting means corresponds to one of the predetermined numbers; and decoding means for decoding the code word identified by the maximum likelihood detecting means to recover a data word.

Claim 11

A demodulator for reproducing data words each being composed of M bits from a channel signal formed of a serial train of code words each being composed of N bits, where N>M, and containing a specific number of `1` bits, said code words being classified into at least two groups such that the number of `1` bits contained in each code word in each of said groups is the same and such that the number of `1` bits contained in each code word in the number of `1` bits contained in each code word in another of said groups, comprising: a plurality of voltage comparating means having different thresholds from one another for waveform shaping the channel signal with the respective thresholds; a plurality of counting means which are respectively coupled to the plurality of voltage comparating means and each of which is for separating an output of a corresponding one of the plurality of voltage comparating means into N-bit words and counting the number of `1` bits contained in each N-bit word; maximum likelihood detecting means for identifying as a code word one having a maximum likelihood from N-bit words in each of which the number counted by the counting means corresponds to one of the predetermined numbers; and decoding means for decoding the code word identified by the maximum likelihood detecting means to recover a data word.

Claim 12

A demodulator as defined in claim 9, wherein the maximum likelihood detecting means recognizes a threshold of the voltage comparating means which is most approximate to a reference value as a likelihood.

Claim 13

A demodulator for reproducing data words each being composed of M bits from a channel signal formed of a serial train of code words each being composed of N bits, where N>M, and containing a specific number of `1` bits, said code words being classified into at least two groups such that the number of `1` bits contained in each code word in each of said groups is the same and such that the number of `1` bits contained in each code word in one of said groups is different by at least 3 from the number of `1` bits contained in each code word in another of said groups, comprising: sampling holding means for sampling the channel signal; analog to digital converter means for converting the sampled values into digital values; sorting means for arranging the digital values in order from the largest value to the smallest value; classifying means for computing a difference between an i-th largest value and an i+1th largest value of the digital values arranged by the sorting means, where i is one of said predetermined numbers, and determining i as the number of `1` bits in the code word when said difference exceeds a specified value; and code word reproducing means for reproducing a code word by recognizing i bits as `1` in the order from the largest likelihood in the digital values.

Claim 14

A demodulator for reproducing data words each being composed of M bits from a channel signal formed of a serial train of code words each being composed of N bits, where N>M, and containing a specific number of `1` bits, said code words being classified into at least two groups such that the number of `1` bits contained in each code word in each of said groups is the same and such that the number of `1` bits contained in each code word in one of said groups is different by at least 3 from the number of `1` bits contained in each code word in another of said groups, comprising: sampling holding means for sampling the channel signal; analog to digital converter means for converting the sampled values into digital values; sorting means for arranging the digital values in order from the largest value to the smallest value; classifying means for computing a difference between an i-th largest value and an i+1th largest value of the digital values arranged by the sorting means, where i is one of said predetermined numbers, and determining i as the number of `1` bits in the code word when said difference exceeds a specified value; and code word reproducing means for reproducing a code word by recognizing i bits as `1` in the order from the largest likelihood in the digital values.