US5017512A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wafer having a dicing area having a step region covered with a conductive layer and method of manufacturing the same
Assignee: Mitsubishi Electric Corp
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Filing: 1990-08-17
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Granted: 1991-05-21
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Expires: 2010-08-17
Abstract
Abstract A conductive layer is formed at the step portion in a dicing line formed vertically and horizontally on a wafer and at a step portion of the region on which a test element for processing control formed inside of the dicing line or an alignment mark are formed, so as to completely cover the step portions. Since the conductive layer does not come off the step portions in subsequent steps, a short circuit of a wiring layer formed on a semiconductor chip region is prevented.
Inventors
- 👤 Hiroshi Takagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:37
CPC Classifications
H; H10; H10W; H10W46/00; H10P; H10P52/00; H10W46/501
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
130 words
A method of processing a wafer formed of a plurality of chip regions defining a dicing area for isolating said chip regions to form individual chips, wherein at least one step region is formed between said chip regions through said dicing area, said method comprising the steps of: forming a conductive layer extending from one chip region to an opposite chip region through said dicing area, said conductive layer overlying said at least one step region; covering said conductive layer on said at least one step region with a resist film; patterning said resist film; and using said resist film as a mask, etching said conductive layer so that only a portion thereof on said at least one step region remains, and subsequently dicing said wafer to form sand chips.
Claim 2
Independent Claim
130 words
A method of processing a wafer formed of a plurality of chip regions defining a dicing area for isolating said chip regions to form individual chips, wherein at least one step region is formed between said chip regions through said dicing area, said method comprising the steps of: forming a conductive layer extending from one chip region to an opposite chip region through said dicing area, said conductive layer overlying said at least one step region; covering said conductive layer on said at least one step region with a resist film; patterning said resist film; and using said resist film as a mask, etching said conductive layer so that only a portion thereof on said at least one step region remains, and subsequently dicing said wafer to form sand chips.
Claim 3
Dependent Claim
27 words
The method of claim 1, wherein said conductive layer is formed on a side wall and only a portion of the top surface of said step region.
Claim 4
Dependent Claim
27 words
The method of claim 1, further comprising a step of covering said step region in said conductive layer with an insulating film harder than the conductive layer.
Claim 5
Independent Claim
156 words
A method of processing a wafer formed of a plurality of chip regions defining a dicing area for isolating said chip regions to form individual chips, wherein a first step region between each of said chip regions and said dicing area, and a second step region formed of the stacked films in said dicing area are formed, said method comprising the steps of: forming a conductive layer extending from one chip region to an opposite chip region through said dicing area and said stacked films, said conductive layer overlying said first step region and said second step region; covering said conductive layer on said first step region and said second step region with a resist film; patterning said resist film; and using said resist film as a mask, etching said conductive layer so that portions thereof on said first step region and said second step region remain, and subsequently dicing said wafer to form sand chips.
Claim 6
Independent Claim
156 words
A method of processing a wafer formed of a plurality of chip regions defining a dicing area for isolating said chip regions to form individual chips, wherein a first step region between each of said chip regions and said dicing area, and a second step region formed of the stacked films in said dicing area are formed, said method comprising the steps of: forming a conductive layer extending from one chip region to an opposite chip region through said dicing area and said stacked films, said conductive layer overlying said first step region and said second step region; covering said conductive layer on said first step region and said second step region with a resist film; patterning said resist film; and using said resist film as a mask, etching said conductive layer so that portions thereof on said first step region and said second step region remain, and subsequently dicing said wafer to form sand chips.
Claim 7
Dependent Claim
33 words
The method of claim 4, further comprising the step of covering said conductive layer on said first step region and said second step region with an insulating film harder than the conductive layer.
Claim 8
Dependent Claim
32 words
The method of claim 4, wherein a semiconductor element is formed in each of said chip regions, and each of said stacked films is a test element for testing said semiconductor element.
Claim 9
Dependent Claim
19 words
The method of claim 4, wherein each of said stacked films comprises an alignment mark for aligning a mask.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-05-20 | 1994-11-19 | 1995-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-20 | 1998-11-19 | 1999-05-21 | $3760.00 | Window Closed / Lapsed |
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