Semiconductor memory device

Claim 2

A semiconductor memory device including a plurality of memory cells organized in a matrix structure and a sense-amplifier circuit for detecting a voltage at a digit line which changes in accordance with the stored information in the memory cell, said sense-amplifier circuit comprising: a first inverter amplifier having its input coupled to said digit line; a first field effect transistor having its gate connected to the output of said first inverter amplifier and its source electrically coupled to said digit line; a second field effect transistor having its source connected to a first power supply terminal and its gate and drain connected to the drain of said first field effect transistor; a third field effect transistor having its gate connected to the drain of said first field effect transistor and its source connected to said first power supply terminal; a fourth field effect transistor having its gate and drain connected to the drain of said third field effect transistor and its source connected to a second power supply terminal; a fifth field effect transistor having its gate connected to the drain of said second field effect transistor, its drain connected to said first power supply terminal and its source connected to one input of a comparison detector; and a sixth field effect transistor having its gate connected to the drain of said third field effect transistor, its drain connected to the source of said fifth field effect transistor and its source connected to said second power supply terminal.

Claim 3

A semiconductor memory device according to claim 1, further comprising a reference voltage generating circuit including a dummy memory cell and a reference sense-amplifier circuit for detecting a voltage at a dummy digit line which changes in accordance with the information in said dummy memory cell, said reference sense-amplifier comprising: a first reference inverter amplifier having its input coupled to said digit line; a first reference field effect transistor having its gate connected to the output of said first reference inverter amplifier and its source electrically coupled to said dummy digit line; a second reference field effect transistor having its source connected to a first power supply terminal and its gate and drain connected to the drain of said first reference field effect transistor; a third reference field effect transistor having its gate connected to the drain of said first reference field effect transistor and its source connected to said first power supply terminal; a fourth reference field effect transistor having its gate and drain connected to the drain of said third reference field effect transistor and its source connected to a second power supply terminal; a fifth reference field effect transistor having its gate connected to the drain of said second reference field effect transistor, its drain connected to said first power supply terminal and its source connected to the other input of said comparison detector; and a sixth reference field effect transistor having its gate connected to the drain of said third reference field effect transistor, its drain connected to the source of said fifth reference field effect transistor and its source connected to said second power supply terminal.

Claim 4

A semiconductor memory device according to claim 1, wherein said third field effect transistor has a gate width to gate length ratio β 3 different from the β R3 of said third reference field effect transistor with a relation of β 3 =k·β R3 (k is a real number).

Claim 5

A semiconductor memory device according to claim 2, wherein said comparison detector is a differential amplifier including a pair of P-channel type field effect transistors and a pair of N-channel type field effect transistors having gates to which the outputs of said sense-amplifier circuit and said reference voltage generating circuit are applied, respectively, and the output of said comparison detector is supplied to a second inverter connected to an output buffer.

Claim 6

A semiconductor memory device according to claim 2, wherein said first power supply terminal and said second power supply terminal are coupled to a constant power potential and a ground potential, respectively, and said second and third field effect transistors and said second reference and third reference field effect transistors are of a P-channel type and said first, fourth to sixth field effect transistors and said first reference, said fourth to sixth reference field effect transistors are of an N-channel type.

Claim 7

A semiconductor memory device according to claim 1, wherein the respective gate width to gate length ratios β 2 and β 3 of said second and third field effect transistors have a relation of β 3 =n 1 ·β 2 where n 1 is a real number larger than one, and the respective gate width to gate length ratios β 4 and β 6 of said fourth and sixth field effect transistors have a relation of β 6 =n 2 ·β 4 where n 2 is a real number larger than one.

Claim 8

A semiconductor memory device including a plurality of memory cells and a sense-amplifier circuit for detecting a voltage at a digit line which changes in accordance with the stored information in the memory cell, said sense-amplifier circuit comprising: a first inverter amplifier having its input coupled to said digit line; a first field effect transistor having its gate connected to the output of said first inverter amplifier and its source electrically coupled to said digit line; a second field effect transistor having its source connected to a first power supply potential and its gate and drain connected to the drain of said first field effect transistor; a third field effect transistor having its gate connected to the drain of said first field effect transistor and its source connected to said first power supply potential; a fourth field effect transistor having its gate and drain connected to the drain of said third field effect transistor and its source connected to a second power supply potential; a fifth field effect transistor having its gate connected to the drain of said second field effect transistor, its drain connected to said first power supply potential and its source connected to an input of a second inverter amplifier as an output of said memory device; and a sixth field effect transistor having its gate connected to the drain of said third field effect transistor, its drain connected to the source of said fifth field effect transistor and its source connected to said second power supply potential.

Claim 9

A semiconductor memory device including a plurality of memory cells and a sense-amplifier circuit for detecting a voltage at a digit line which changes in accordance with the stored information in the memory cell, said sense-amplifier circuit comprising: a first inverter amplifier having its input coupled to said digit line; a first field effect transistor having its gate connected to the output of said first inverter amplifier and its source electrically coupled to said digit line; a second field effect transistor having its source connected to a first power supply potential and its gate and drain connected to the drain of said first field effect transistor; a third field effect transistor having its gate connected to the drain of said first field effect transistor and its source connected to said first power supply potential; a fourth field effect transistor having its gate and drain connected to the drain of said third field effect transistor and its source connected to a second power supply potential; a fifth field effect transistor having its gate connected to the drain of said second field effect transistor, its drain connected to said first power supply potential and its source connected to an input of a second inverter amplifier as an output of said memory device; and a sixth field effect transistor having its gate connected to the drain of said third field effect transistor, its drain connected to the source of said fifth field effect transistor and its source connected to said second power supply potential.

Claim 10

A semiconductor memory device according to claim 7, wherein said fifth field effect transistor is formed of an N-channel non-doped type, and the ratio α between the gate width to gate length of said fifth field effect transistor and that of said sixth field effect transistor is set at a large value so as to increase the amplitude of the output voltages of said sense-amplifier circuit.

Claim 11

A semiconductor memory device according to claim 7, wherein said first power supply potential and said second power supply potential are a constant supply voltage and a ground potential, respectively, and said second and third field effect transistor are of a P-channel type and said first and fourth to sixth field effect transistors are of an N-channel type.