Depletion mode chip decoupling capacitor

Claim 1

A semiconductor circuit device in which a plurality of active circuit devices are arrayed on a semiconductive substrate in a CMOS configuration, and a plurality of conductive lines extend along the substrate between the active devices and external connection points on the die containing the semiconductor substrate, within a package containing external connection conductors extending within the package from the external connection points and having a significant inductive characteristics, characterized by: a) at least one well consisting of a material of opposite conductivity type as the substrate, achieved by doping to provide an opposite difference from four valence electrons as the substrate; b) a capacitor defined by an active area of the substrate and a polysilicon layer; c) the capacitor being provided with a barrier to substrate, the barrier consisting of a material of opposite conductivity type as the substrate, achieved by providing said capacitor within said well which had been doped to provide an opposite difference from four valence electrons as the substrate, whereby said doped well forms said barrier, the barrier being located in the substrate under the polysilicon layer of the capacitor and under the active area of the substrate at the capacitor as latchup protection; d) the capacitor occupying a space defined by a plurality of the conductive lines; e) the capacitor being in electrical communication with at least one of said lines, wherein the capacitor is located on the substrate in an area which is unoccupied by said active circuit devices, wherein one node is tied directly to substrate and the other node to one of said plurality of conductive lines as an on-chip power bus decoupling capacitor, thereby adding filter capacitance to the semiconductor circuit device in order to provide protection from voltage transients which may occur at the external connection points as a result of said inductive characteristics of the external connection conductors; f) said conductive lines being circuit busses for circuits on the semiconductor device; g) said conductive lines being metal conductors; h) one of said conductive lines being maintained at a regulated potential; i) an additional capacitor located on the substrate in an area which is unoccupied by said active circuit device and connected in series with said capacitor in electrical communication with said conductive line which is maintained at the regulated potential; and j) the additional capacitor sharing a common electrode plate which extends across said unoccupied area between the two capacitors.