US5033024A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Matrix memory with redundancy and minimizes delay
Assignee: NXP BV
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Filing: 1989-12-20
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Granted: 1991-07-16
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Expires: 2009-12-20
Abstract
Abstract An integrated matrix memory includes standard sub-blocks and a redundant block. Each of the standard sub-blocks has a fixed number of standard sub-blocks, and the redundant block has one or more redundant sub-blocks. For addressing there is provided a detector for the address of a faulty standard sub-block. In that case a redundant sub-block is selected. Selection is realized by way of a sub-bus which forms part of the data path. Thus, a redundant system is achieved in which delay is minimized.
Inventors
- 👤 Cormac M. O'Connell
- 👤 Leonardus Pfennings, deceased
- 👤 executor by Henricus J. Kunnen
- 👤 Peter H. Voss
- 👤 Thomas J. Davies
- 👤 Hans Ontrop
- 👤 Cathal G. Phelan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:07
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/84; G11C29/846
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
167 words
An integrated matrix memory, comprising a series of p standard blocks, each of which comprises a uniform first number of i standard sub-blocks, each of which comprises a uniform second number of n storage columns, each sub-block in any block being connected, via a column selector, to a sub-bus which is exclusively assigned to each respective sub-block within the latter block and which also serves for further sub-blocks of the same rank in other blocks, a bus selector provided between respective sub-buses and an external data terminal, a redundant block which comprises a third number of j redundant sub-blocks, each of which comprises n storage columns, each of which is connected to a respective sub-bus via a further column selector, and error address detector means for detecting an error address concerning a faulty standard sub-block and for activating in response thereto said redundant block, and also said redundant sub-block therein which is known in advance by selective activation of the sub-bus connected to the relevant redundant sub-block.
Claim 2
Dependent Claim
167 words
An integrated matrix memory, comprising a series of p standard blocks, each of which comprises a uniform first number of i standard sub-blocks, each of which comprises a uniform second number of n storage columns, each sub-block in any block being connected, via a column selector, to a sub-bus which is exclusively assigned to each respective sub-block within the latter block and which also serves for further sub-blocks of the same rank in other blocks, a bus selector provided between respective sub-buses and an external data terminal, a redundant block which comprises a third number of j redundant sub-blocks, each of which comprises n storage columns, each of which is connected to a respective sub-bus via a further column selector, and error address detector means for detecting an error address concerning a faulty standard sub-block and for activating in response thereto said redundant block, and also said redundant sub-block therein which is known in advance by selective activation of the sub-bus connected to the relevant redundant sub-block.
Claim 3
Dependent Claim
68 words
A matrix memory as claimed in claim 1, further comprising a block decoder which is subdivided into a predecoder and a main decoder, said error address detector means being fed by output signals of the predecoder and also by primary sub-bus selection signals in order to activate, upon detection of said error address, secondary sub-bus selection signals as substitutes for primary sub-bus selection signals prevailing at that instant.
Claim 4
Dependent Claim
23 words
A matrix memory as claimed in claim 2, characterized in that said primary sub-bus section signals are supplied by a sub-bus selection decoder.
Claim 5
Dependent Claim
29 words
A matrix memory as claimed in claim 1 or 2, characterized in that the number of redundant sub-blocks is smaller than the number of standard sub-blocks per standard block.
Claim 6
Dependent Claim
30 words
A matrix memory as claimed in claim 1, 2 or 3, characterized in that the number of redundant sub-blocks is equal to the number of standard sub-blocks per standard block.
Claim 7
Dependent Claim
26 words
A matrix memory as claimed in claim 1, 2 or 3, characterized in that the column selector selects a single column from the associated standard/redundant sub-block.
Claim 8
Dependent Claim
28 words
An integrated circuit, comprising a second series of matrix memories as claimed in claim 1, 2 or 3, each matrix memory comprising a separately-adjustable error address detector means.
References Cited (Backward Citations)
US4599709A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-15 | 1995-01-14 | 1995-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-15 | 1999-01-14 | 1999-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-15 | 2003-01-14 | 2003-07-16 | $7700.00 | Window Closed / Lapsed |