US5042013A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory
Assignee: Micron Memory Japan Ltd
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Filing: 1990-01-30
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Granted: 1991-08-20
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Expires: 2010-01-30
Abstract
Abstract A semiconductor memory of a dual-port type formed on one semiconductor chip used for image processing which has input/output circuits and which has respective semiconductor memory units having a memory array of rows and columns of memory cells, a plurality of sense amplifiers coupled to one end of the memory array data lines and being respectively associated with individual pairs of complementary data lines, a row address decoder for selectively applying signals to the word lines, column switches for providing either selective or simultaneous connection of the plurality of complementary pairs of data lines to a pair of complementary common data lines, write amplifiers for supplying predetermined write signals to respective data lines via the common data lines and column switches, the sense amplifiers becoming operational during a predetermined mode of operation subsequent to the transfer of write signals to the data lines and the write signals being supplied from the write amplifiers are, furthermore, made to have a minute level equal to or greater than that of a typical readout signal from a memory cell.
Inventors
- 👤 Katsuyuki Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 00:01
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
254 words
A semiconductor memory device formed on one chip used for image processing comprising: a memory array comprised of a plurality of data lines and word lines disposed in an arrangement of perpendicularly intersecting data lines and word lines and a plurality of memory cells respectively disposed like a lattice at intersections of said data lines and word lines for storing image data; a plurality of sense amplifiers, wherein each one is coupled to a respective data line, and wherein said plurality of sense amplifiers are electively placed in an operational state in accordance with a predetermined timing signal; a row address decoder providing word line signals at selected word lines thereby placing them in a selected state condition; a column switch circuit being coupled between said plurality of data lines and a common data line for providing selective or simultaneous connection of said plurality of data lines to said common data line; an input circuit including a write amplifier having an output coupled to said common data line, wherein said write amplifier supplies predetermined write signals to data lines brought into a state of connection with said common data line via said column switch circuit; and a serial output circuit including a parallel to serial converter coupled to said plurality of data lines, wherein said sense amplifiers are placed in an operational state after a write signal is supplied from said write amplifier to data lines which are brought, via said column switch circuit, into a state of connection to said common data line.
Claim 2
Dependent Claim
254 words
A semiconductor memory device formed on one chip used for image processing comprising: a memory array comprised of a plurality of data lines and word lines disposed in an arrangement of perpendicularly intersecting data lines and word lines and a plurality of memory cells respectively disposed like a lattice at intersections of said data lines and word lines for storing image data; a plurality of sense amplifiers, wherein each one is coupled to a respective data line, and wherein said plurality of sense amplifiers are electively placed in an operational state in accordance with a predetermined timing signal; a row address decoder providing word line signals at selected word lines thereby placing them in a selected state condition; a column switch circuit being coupled between said plurality of data lines and a common data line for providing selective or simultaneous connection of said plurality of data lines to said common data line; an input circuit including a write amplifier having an output coupled to said common data line, wherein said write amplifier supplies predetermined write signals to data lines brought into a state of connection with said common data line via said column switch circuit; and a serial output circuit including a parallel to serial converter coupled to said plurality of data lines, wherein said sense amplifiers are placed in an operational state after a write signal is supplied from said write amplifier to data lines which are brought, via said column switch circuit, into a state of connection to said common data line.
Claim 3
Dependent Claim
66 words
A semiconductor memory device according to claim 1, wherein each one of said plurality of data lines and said common data line are comprised of a pair of complementary signal lines, and wherein said write signal outputted from said write amplifier is of a potential level substantially equal to or greater than that of read-out signals outputted from memory cells brought into a state of selection.
Claim 4
Dependent Claim
44 words
A semiconductor memory device according to claim 2, wherein said column switch circuit comprises a plurality of pairs of switches, each pair of switches being disposed between a corresponding pair of complementary data signal lines and the pair of complementary common data signal lines.
Claim 5
Dependent Claim
93 words
A semiconductor memory device according to claim 3, wherein each one of said plurality of pairs of switches is connected as a pair of transmission switches and includes a pair of MOSFETs each one coupling, via the source-to-drain path thereof, a respective signal line of a corresponding data complementary pair of signal lines to a respective signal line of the common data complementary pair of signal lines, the gates of each such pair of MOSFETs being commonly coupled for receiving a corresponding data line selecting signal in accordance with a data line address.
Claim 6
Dependent Claim
36 words
A semiconductor memory device according to claim 4, wherein said write amplifier is associated with a random access port of a dual port memory which includes both said random access port and a serial access port.
Claim 7
Dependent Claim
111 words
A semiconductor memory device according to claim 5, wherein a plurality of memory arrays are included, each one being correspondingly associated with a respective column switch circuit and a respective plurality of sense amplifiers corresponding in number to the number of data lines of the corresponding memory array, a respective common data line and a respective write amplifier which supplies predetermined write signals, in accordance with externally supplied data write signals, to data lines brought into a state of connection with the corresponding common data line via the corresponding column switch circuit, either selectively in response to a normal write operation mode or simultaneously in response to a clear operation mode.
Claim 8
Dependent Claim
88 words
A semiconductor memory device according to claim 1, wherein said parallel to serial converter is associated with a serial access port which includes a data register having a plurality of parallelly disposed latch circuit coupling said plurality of sense amplifiers via a data selector and a data output buffer of a serial input/output circuit to an external data terminal, and a shift register loop circuit for controlling start-up and accessing of memory array data lines in accordance with select signals from a serial access port column address decoder.
Claim 9
Dependent Claim
42 words
A semiconductor memory device according to claim 7, wherein said serial input/output circuit further includes a data input buffer and an amplifier, in series therewith between said external data terminal and said data selector via a serial input/output complementary common data line.
Claim 10
Dependent Claim
254 words
A semiconductor memory device formed on one chip used for image processing comprising: a memory array comprised of a plurality of data lines and word lines disposed in an arrangement of perpendicularly intersecting data lines and word lines, and a plurality of memory cells respectively disposed like a lattice at intersections of said data lines and word lines; a plurality of sense amplifiers, wherein each one is coupled to a respective data line, and wherein said plurality of sense amplifiers are selectively placed in an operational state in accordance with a predetermined timing signal; a row address decoder providing a word line signal at a selected word line thereby placing it in a selected state condition; a column switch circuit being coupled between said plurality of data lines and a common data line for providing selective or simultaneous connection of said plurality of data lines to said common data line; an input circuit including a write amplifier having an output coupled to said common data line, wherein said write amplifier supplies predetermined write signals to data lines brought into a state of connection with said common data line via said column switch circuit; and a serial output circuit including a parallel to serial converter coupled to said plurality of data lines, wherein said selected word line is placed in a selected state condition after a write signal is supplied from said write amplifier to date lines which are brought, via said column switch circuit, into a state of connection with said common data line.
Claim 11
Dependent Claim
254 words
A semiconductor memory device formed on one chip used for image processing comprising: a memory array comprised of a plurality of data lines and word lines disposed in an arrangement of perpendicularly intersecting data lines and word lines, and a plurality of memory cells respectively disposed like a lattice at intersections of said data lines and word lines; a plurality of sense amplifiers, wherein each one is coupled to a respective data line, and wherein said plurality of sense amplifiers are selectively placed in an operational state in accordance with a predetermined timing signal; a row address decoder providing a word line signal at a selected word line thereby placing it in a selected state condition; a column switch circuit being coupled between said plurality of data lines and a common data line for providing selective or simultaneous connection of said plurality of data lines to said common data line; an input circuit including a write amplifier having an output coupled to said common data line, wherein said write amplifier supplies predetermined write signals to data lines brought into a state of connection with said common data line via said column switch circuit; and a serial output circuit including a parallel to serial converter coupled to said plurality of data lines, wherein said selected word line is placed in a selected state condition after a write signal is supplied from said write amplifier to date lines which are brought, via said column switch circuit, into a state of connection with said common data line.
Claim 12
Dependent Claim
66 words
A semiconductor memory device according to claim 9, wherein each one of said plurality of data lines and said common data line are comprised of a pair of complementary signal lines, and wherein said write signal outputted from said write amplifier is of a potential level substantially equal to or greater than that of read-out signals outputted from memory cells brought into a state of selection.
Claim 13
Dependent Claim
44 words
A semiconductor memory device according to claim 10, wherein said column switch circuit comprises a plurality of pairs of switches, each pair of switches being disposed between a corresponding pair of complementary data signal lines and the pair of complementary common data signal lines.
Claim 14
Dependent Claim
93 words
A semiconductor memory device according to claim 11, wherein each one of said plurality of pairs of switches is connected as a pair of transmission switches and includes a pair of MOSFETs each one coupling, via the source-to-drain path thereof, a respective signal line of a corresponding data complementary pair of signal lines to a respective signal line of the common data complementary pair of signal lines, the gates of each such pair of MOSFETs being commonly coupled for receiving a corresponding data line selecting signal in accordance with a data line address.
Claim 15
Dependent Claim
36 words
A semiconductor memory device according to claim 12, wherein said write amplifier is associated with a random access port of a dual port memory which includes both said random access port and a serial access port.
Claim 16
Dependent Claim
111 words
A semiconductor memory device according to claim 13, wherein a plurality of memory arrays are included, each one being correspondingly associated with a respective column switch circuit and a respective plurality of sense amplifiers corresponding in number to the number of data lines of the corresponding memory array, a respective common data lines and a respective write amplifier which supplies predetermined write signals, in accordance with externally supplied data write signals, to date lines brought into a state of connection with the corresponding common data line via the corresponding column switch circuit, either selectively in response to a normal write operation mode or simultaneously in response to a clear operation mode.
Claim 17
Independent Claim
106 words
A method of writing data to a memory cell in a semiconductor memory having a data line and a word line coupled to said memory cell, respectively, a sense amplifier coupled to said data line, a write amplifier coupled to said data line and a column switch coupled between said write amplifier and said data line, comprising the steps of: (a) supplying a write signal from said write amplifier to said data line via said column switch; (b) placing said sense amplifier in an operational state for amplifying said write signal; and (c) storing said write signal, amplified by said sense amplifier, to said memory cell.
Claim 18
Independent Claim
106 words
A method of writing data to a memory cell in a semiconductor memory having a data line and a word line coupled to said memory cell, respectively, a sense amplifier coupled to said data line, a write amplifier coupled to said data line and a column switch coupled between said write amplifier and said data line, comprising the steps of: (a) supplying a write signal from said write amplifier to said data line via said column switch; (b) placing said sense amplifier in an operational state for amplifying said write signal; and (c) storing said write signal, amplified by said sense amplifier, to said memory cell.
Claim 19
Dependent Claim
24 words
A method according to claim 15, further including the step of: placing said word line in a selected state condition before said step (b).
Claim 20
Dependent Claim
158 words
A semiconductor memory comprising: at least a pair of data signal lines; a plurality of memory cells respectively having selection terminals and having input/output terminals thereof coupled to one of said data signal lines, respectively; a plurality of word lines respectively coupled to selection terminals of said memory cells which are correspondingly associated therewith; a sense amplifier coupled to said pair of data signal lines; a pair of switches coupled between each pair of said at least a pair of data signal lines and a pair of common data signal lines; and a write amplifier having an output coupled to said pair of common data signal lines, wherein said sense amplifier is placed in an operational state after a write signal is supplied from said write amplifier to said pair of data lines via said pair of common data lines and said pair of switches and after one of said word lines is placed in a selected state.
Claim 21
Dependent Claim
158 words
A semiconductor memory comprising: at least a pair of data signal lines; a plurality of memory cells respectively having selection terminals and having input/output terminals thereof coupled to one of said data signal lines, respectively; a plurality of word lines respectively coupled to selection terminals of said memory cells which are correspondingly associated therewith; a sense amplifier coupled to said pair of data signal lines; a pair of switches coupled between each pair of said at least a pair of data signal lines and a pair of common data signal lines; and a write amplifier having an output coupled to said pair of common data signal lines, wherein said sense amplifier is placed in an operational state after a write signal is supplied from said write amplifier to said pair of data lines via said pair of common data lines and said pair of switches and after one of said word lines is placed in a selected state.
Claim 22
Dependent Claim
51 words
A semiconductor memory according to claim 17, further comprising: precharge means for setting said pair of data lines and said pair of common data lines to an intermediate level of a signal to be stored in said memory cells before said write signal is supplied to said pair of data lines.
Claim 23
Dependent Claim
45 words
A semiconductor memory according to claim 18, wherein each pair of data signal lines of said at least a pair of data signal lines and said pair of common data signal lines correspond to a complementary data line and a complementary common data line, respectively.
Claim 24
Dependent Claim
35 words
A semiconductor memory according to claim 19, wherein said write amplifier is associated with a random access port of a dual port memory which includes both said random access port and a serial access port.
References Cited (Backward Citations)
US4916669A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-19 | 1995-02-18 | 1995-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-19 | 1999-02-18 | 1999-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-19 | 2003-02-18 | 2003-08-20 | $7700.00 | Window Closed / Lapsed |