High-voltage generating circuit having improved voltage boosting efficiency

Claim 1

A higher voltage generating circuit comprising a power voltage terminal receiving a power voltage, an output terminal, a series circuit of first to (N+1)th field effect transistors wherein N is a positive integer of 2 or more, said field effect transistors having drain-source paths connected in series between said power voltage terminal and said output terminal, a gate and a drain of said first transistor being connected to said power voltage terminal, gates and drains of said second to (N+1)th transistors being connected to sources of the following transistors in said series circuit at first to Nth nodes, respectively, first to Nth capacitors having first ends coupled to said first to Nth nodes, respectively, clock signal generating circuit means for generating a first clock signal having a pulse height of a high voltage which is larger than said power voltage and having a first phase and a second clock signal having said pulse height but having a second phase different from said first phase, first means for applying said first clock signal to second ends of the odd numbers of said capacitors, and second means for applying said second clock signal to second ends of the even numbers of said capacitors, wherein each of said first and second clock signal is generated, respectively, by a clock generating circuit including first and second transfer field effect transistors connected in series between said power voltage terminal and an output end, a charge capacitor having a first end connected to said output end and a clamp field effect transistor connected between said output end and a voltage node receiving a reference voltage.