Non-volatile memory

Claim 2

A non-volatile memory comprising: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply and; a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region.

Claim 3

A non-volatile memory according to claim 1 wherein said programming field effect transistor additionally includes a switching element connected in series thereto.

Claim 4

A non-volatile memory according to claim 1, wherein the non-volatile memory is coupled to an integrated circuit.

Claim 5

An integrated circuit including a non-volatile memory, characterized in that the non-volatile memory comprises: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manners against the interruption of the power supply; a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region.

Claim 6

An integrated circuit including a non-volatile memory, characterized in that the non-volatile memory comprises: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manners against the interruption of the power supply; a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region.

Claim 7

A non-volatile memory comprising: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor and said programming field effect transistor being connected to each other at their control gate electrodes and being earthened at their source regions, the drain region of said latching field effect transistor being connected to a first terminal of said load element, said load element being connected to the power supply at a second terminal thereof different from said first terminal.

Claim 8

A non-volatile memory comprising: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor and said programming field effect transistor being connected to each other at their control gate electrodes and being earthened at their source regions, the drain region of said latching field effect transistor being connected to a first terminal of said load element, said load element being connected to the power supply at a second terminal thereof different from said first terminal.

Claim 9

A non-volatile memory comprising: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor having a structure to prevent hot electrons from being produces in a channel region thereof.

Claim 10

A non-volatile memory comprising: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor having a structure to prevent hot electrons from being produces in a channel region thereof.

Claim 11

A non-volatile memory comprising: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor having a structure to prevent hot electrons produces in a channel region thereof from being injected into the floating gate electrode thereof.

Claim 12

A non-volatile memory comprising: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor having a structure to prevent hot electrons produces in a channel region thereof from being injected into the floating gate electrode thereof.

Claim 13

A non-volatile memory comprising: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor having a structure to reduce a leakage current produced between a source and the drain thereof or between the drain thereof and a body.

Claim 14

A non-volatile memory comprising: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor having a structure to reduce a leakage current produced between a source and the drain thereof or between the drain thereof and a body.

Claim 15

A non-volatile memory comprising: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor being of an LDD structure which has second conductivity type regions with lower concentration than second conductivity type source and drain regions on the surface of a first conductivity type substrate making contact with the channel region thereof.

Claim 16

A non-volatile memory comprising: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor being of an LDD structure which has second conductivity type regions with lower concentration than second conductivity type source and drain regions on the surface of a first conductivity type substrate making contact with the channel region thereof.

Claim 17

A non-volatile memory comprising: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said signal hold circuit additionally including a capacitor for assisting an information storing action between a signal hold node and the ground.

Claim 18

A non-volatile memory comprising: a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said signal hold circuit additionally including a capacitor for assisting an information storing action between a signal hold node and the ground.